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Terasic Atum A5 User Manual

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Atum A5
Atum A5
Development Kit
Development Kit
Higher Speed, Richer Interfaces with
Cutting Edge AI features based on
Intel Agilex 5 SoC FPGA !
User Manual
© Copyright Terasic Inc. All Rights Reserved

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Summary of Contents for Terasic Atum A5

  • Page 1 Atum A5 Atum A5 Development Kit Development Kit Higher Speed, Richer Interfaces with Cutting Edge AI features based on Intel Agilex 5 SoC FPGA ! User Manual © Copyright Terasic Inc. All Rights Reserved...

  • Page 2: Table Of Contents

    General User I/O ................. 24 2x20 GPIO Expansion Header ............27 Micro SD Card and eMMC ..............29 FMC+ Connector ................. 31 USB to UART ..................48 2.10 DDR4 SDRAM ..................51 Atum A5 www.terasic.com User Manual June 24, 2024...
  • Page 3 Install Driver for the Board ..........88 Install the USB Blaster II Driver ............88 Install USB to UART Driver ..............88 Chapter 5 Additional Information ............89 Getting Help ..................89 www.terasic.com Atum A5 User Manual June 24, 2024...

  • Page 4: Chapter 1 Overview

    With a rich set of interfaces ranging from 2.5G Ethernet, high-speed DDR4, QSFP+, PCIe Gen 3x4, FMC+ connectors, to MIPI connector and HDMI, the Atum A5 excels in a wide range of applications, including industrial networking, AI, embedded vision,...

  • Page 5: Board Layout

    The figures below depict the layout of the board and indicate the location of the connectors and key components. Figure 1-2 Atum A5 board top Key Features The following hardware is implemented on the Atum A5 board:  FPGA Device Intel® Agilex™ 5 SoC FPGA : A5ED065BB32AE4SR0 ...

  • Page 6: Fpga Configuration

     LED x1, Button x1, Cold Reset Button  One 3.3V 2x6 GPIO Header. Including One I2C Bus   Dashboard System Power Monitor  Temperature Monitor  Auto Fan Control  www.terasic.com Atum A5 User Manual June 24, 2024...

  • Page 7: Block Diagram

    Thus, users can configure the FPGA to implement any system design. Figure 1-3 Block diagram of the Atum A5 board 1.4. Mechanical Specifications Figure 1-4 shows the Mechanical Layout of Atum A5 board. The unit of the Mechanical Layout is millimeter (mm). www.terasic.com Atum A5...
  • Page 8 Figure 1-4 Mechanical layout www.terasic.com Atum A5 User Manual June 24, 2024...

  • Page 9: Chapter 2 Board Component

    Configuration Interface This section describes the configuration mode for Agilex SoC FPGA available on the Atum A5. The peripheral circuits and usage scenarios for each mode will be listed. Figure 2-1, the mode select pin of the FPGA on the Atum A5 board has...
  • Page 10 QSPI flash to configure the FPGA including FPGA I / O and core configuration. HPS part of the boot can also be completed in this mode. Figure 2-2 shows the architecture of the AS mode of the Atum A5 board. Figure 2-2 AS mode for the Atum A5 board www.terasic.com Apollo-Agilex SoM...
  • Page 11 FPGA fabric after powering on. More details can be found in the user documentation: Hard Processor System Booting User Guide: Agilex 5 SoCs. The factory setting of the SoC boot of the Atum A5 board is the FPGA Configuration First Mode. The architecture is shown in the Figure 2-3.

  • Page 12: Jtag Programming

    Finally, the OS boots and applications are scheduled for runtime launch.  JTAG Programming The JTAG interface of the Atum A5 is mainly implemented by the USB Blaster II circuit on the board. For programming by on-board USB Blaster II, the following procedures...

  • Page 13: Setup And Status Components

    FPGA programming. Setup and Status Components This section will introduce the use of the switch for setup on the Atum A5 board, as well as a description of the various status LEDs.  Status LED The FPGA development board includes board-specific status LEDs to indicate board status.
  • Page 14 FPGA. As currently only AS Fast and JTAG mode are supported. If SW4 is set to AS fast mode. When the board power up, the Secure Device Manager (SDM) in the FPGA will boot from the Quad SPI flash. www.terasic.com Apollo-Agilex SoM User Manual...
  • Page 15 OFF position, but does not connect the JTAG device on the FMC+ connector. The JTAG chain on the Atum A5 board will not be able to form a closed loop and Quartus will not be able to detect the FPGA device.
  • Page 16 SW27 on the board can help the user select which device (Micro SD Card or eMMC) will be used for HPS fabric. Figure 2-7 shows the position of the SW27. Table 2-4 list the setting for the JP1 www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...
  • Page 17 Note that only one switch can be set to the on position at a time. Figure 2-8 shows the position of this switch on the Table 2-5 board. list the setting for each switch. www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...
  • Page 18 Figure 2-9 Table 2-6). This function can be achieved because the VCCIO power pin of the FPGA bank where these FPGA I/Os are located can adjust the input voltage through the 3 pin www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...
  • Page 19 Table 2-6 FPGA I/Os on the FMC+ connector which can be changed I/O standard to 1.2 or 1.3V FMC Pins which can modify I/O stadnard FMCP_HA_p[23..0] FMCP_HA_n[23..0] FMCP_HB_p[21..0] FMCP_HB_p[21..0] FMCP_CLK_M2C_p[1..0] FMCP_CLK_M2C_n[1..0] FMCP_SYNC_M2C_p FMCP_SYNC_M2C_n www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...

  • Page 20: Reset Devices

    The board provides 3 reset buttons for different system reset situations (see Figure 2-11). These buttons can reset FPGA, System MAX, HPS and FPGA respectively. Please refer to the following Table 2-8 for details. www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...
  • Page 21 Signal Name Standard Number This button can be used for rest 3.3-V CPU_RESET_n PIN_ BF104 FPGA (Need LVCMOS user setting or logic) For resetting MAX_RESET_n System MAX10 For resetting HPS_COLD_RESET_N System HPS Fabric www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...

  • Page 22: Clock Circuit

    Ethernet and USB3.1 interfaces on the board. Users can also modify the output frequency through the I2C interface. For memory interface, the board provides a 150Mhz clock and fan out it to two Apollo-Agilex SoM www.terasic.com User Manual June 24, 2024...
  • Page 23 150 Mhz Differential PIN_AC68 reference Buffer Signaling clock 2.5G High Speed ENET_88E2110_REFCLK_125M_p 125MHz PIN_AT13 Ethernet Differential I/O Interface HPS_USB3_REFCLK_100M_p 100Mhz PIN_AP120 USB3.1 Si5340B Interface True User CLK_100_B2B_p 100 Mhz Differential PIN_BF68 application Signaling www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...

  • Page 24: General User I/O

    HPS and FPGA portions of the device each have their own pins. Pins are not freely shared between the HPS and the FPGA fabric. Figure 2-13 shows the position of all these components and interface. www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...

  • Page 25: User Defined Push-Buttons

    FPGA Pin Description Reference Signal Name Standard Number BUTTON0 3.3 V PIN_H8 BUTTON1 3.3 V PIN_C2 High Logic Level when the BUTTON2 button is not pressed 3.3 V PIN_D4 BUTTON3 3.3 V PIN_F4 www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...

  • Page 26: User-Defined Dip Switch

    FPGA that are connected to the LEDs is given in Table 2-14 list the information of the LED for the HPS fabric. Table 2-13 User LEDs (FPGA fabric) Pin Assignments, Schematic Signal Names www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...

  • Page 27: 2X20 Gpio Expansion Header

    Each pin on the expansion headers is connected to two diodes and a resistor for protection against high or low voltage level. Figure 2-14 shows the protection circuitry applied to all 36 data pins. Table 2-16 shows the pin assignment of the GPIO header. www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...
  • Page 28 3.3-V PIN_BU22 GPIO[11] GPIO Connection[11] 3.3-V PIN_BR22 GPIO[12] GPIO Connection[12] 3.3-V PIN_BM19 GPIO[13] GPIO Connection[13] 3.3-V PIN_BM22 GPIO[14] GPIO Connection[14] 3.3-V PIN_BK19 GPIO[15] GPIO Connection[15] 3.3-V PIN_BK22 GPIO[16] GPIO Connection[16] 3.3-V PIN_BH19 www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...

  • Page 29: Micro Sd Card And Emmc

    HPS fabric. The Micro SD card socket can provide flexible capacity expansion while eMMC device can support stable and fixed storage solutions. Table 2-17 lists the pin assignment of Micro SD card socket and eMMC device to the HPS. www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...
  • Page 30 FPGA Pin Description Signal Name Standard Number HPS_SDMMC_CLK HPS SD/eMMC Clock 1.8-V PIN_D132 HPS_SDMMC_CMD HPS SD/eMMC Command Line 1.8-V PIN_AB132 HPS_SDMMC_DATA[0] HPS SD/eMMC Data[0] 1.8-V PIN_E135 HPS_SDMMC_DATA[1] HPS SD/eMMC Data[1] 1.8-V PIN_F132 www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...

  • Page 31: Fmc+ Connector

    I/O (transceivers), and single-ended or differential signaling. There FMC+ connector on the Atum A5 board is a High Pin Count (HPC) size of connector, The HPC connector on Atum A5 board can provides 169 user-define, single- ended signals (80 pair differential I/O) and 12 serial transceiver pairs.
  • Page 32 PIN_BU49 Power Supply  The Atum A5 board provides 12V, 3.3V and 1.2V(VADJ) power through FMC+ ports. Table 2-19 indicates the maximum power consumption for the FMC+ connector. CAUTION: Before powering on the Atum A5 board with a daughter card, please check to see if there is a short circuit between the power pins and FMC+ FPGA I/O.
  • Page 33 JTAG device on the user's FMC+ daughter card can be joined with JTAG chain on the Atum A5 board. Users can enable this feature through the switch (SW31) on the Atum A5 board. In the board's default setting, the JTAG interface of the FMC+ connector is bypassed to keep the Atum A5 board JTAG chain to maintain close loop.
  • Page 34 FPGA Pin Assignments for FMC+ Connector  Figure 2-18 shows the pin out table of the FMC+ connector on the Atum A5 and 錯誤! 找不 到參照來源。 lists the FMC+ connector pin assignments, signal names and functions. Figure 2-18 FMC+ pin out table...
  • Page 35 FMCP HA bank FMCP_HA_p[5] PIN_BU59 1.2 V/1.3 data p5 FMCP HA bank FMCP_HA_p[6] PIN_BH69 1.2 V/1.3 data p6 FMCP HA bank FMCP_HA_p[7] PIN_CH69 1.2 V/1.3 data p7 FMCP_HA_p[8] PIN_CF59 FMCP HA bank 1.2 V/1.3 www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...
  • Page 36 FMCP HA bank FMCP_HA_p[21] PIN_BF93 1.2 V/1.3 data p21 FMCP HA bank FMCP_HA_p[22] PIN_BF86 1.2 V/1.3 data p22 FMCP HA bank FMCP_HA_p[23] PIN_BE96 1.2 V/1.3 data p23 FMCP_HA_n[0] PIN_BK69 FMCP HA bank 1.2 V/1.3 www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...
  • Page 37 FMCP HA bank FMCP_HA_n[13] PIN_CH62 1.2 V/1.3 data n13 FMCP HA bank FMCP_HA_n[14] PIN_CA71 1.2 V/1.3 data n14 FMCP HA bank FMCP_HA_n[15] PIN_CH71 1.2 V/1.3 data n15 FMCP_HA_n[16] PIN_BR62 FMCP HA bank 1.2 V/1.3 www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...
  • Page 38 FMCP HB bank FMCP_HB_p[5] PIN_CF81 1.2 V/1.3 data p5 FMCP HB bank FMCP_HB_p[6] PIN_BR92 1.2 V/1.3 data p6 FMCP HB bank FMCP_HB_p[7] PIN_BH89 1.2 V/1.3 data p7 FMCP_HB_p[8] PIN_CH89 FMCP HB bank 1.2 V/1.3 www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...
  • Page 39 FMCP HB bank FMCP_HB_p[21] PIN_CF92 1.2 V/1.3 data p21 FMCP HB bank FMCP_HB_n[0] PIN_BU81 1.2 V/1.3 data n0 FMCP HB bank FMCP_HB_n[1] PIN_CA78 1.2 V/1.3 data n1 FMCP_HB_n[2] PIN_CK94 FMCP HB bank 1.2 V/1.3 www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...
  • Page 40 FMCP HB bank FMCP_HB_n[15] PIN_CL85 1.2 V/1.3 data n15 FMCP HB bank FMCP_HB_n[16] PIN_CC81 1.2 V/1.3 data n16 FMCP HB bank FMCP_HB_n[17] PIN_BK78 1.2 V/1.3 data n17 FMCP_HB_n[18] PIN_BH78 FMCP HB bank 1.2 V/1.3 www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...
  • Page 41 FMCP LA bank 1.2 V FMCP_LA_p[9] PIN_CF19 data p9 FMCP LA bank 1.2 V FMCP_LA_p[10] PIN_CF22 data p10 FMCP LA bank 1.2 V FMCP_LA_p[11] PIN_BM52 data p11 FMCP_LA_p[12] PIN_BP41 FMCP LA bank 1.2 V www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...
  • Page 42 FMCP LA bank 1.2 V FMCP_LA_p[25] PIN_CH41 data p25 FMCP LA bank 1.2 V FMCP_LA_p[26] PIN_CK39 data p26 FMCP LA bank 1.2 V FMCP_LA_p[27] PIN_CK35 data p27 FMCP_LA_p[28] PIN_CC52 FMCP LA bank 1.2 V www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...
  • Page 43 FMCP LA bank 1.2 V FMCP_LA_n[7] PIN_BF64 data n7 FMCP LA bank 1.2 V FMCP_LA_n[8] PIN_BF46 data n8 FMCP LA bank 1.2 V FMCP_LA_n[9] PIN_CC19 data n9 FMCP_LA_n[10] PIN_CH22 FMCP LA bank 1.2 V www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...
  • Page 44 FMCP LA bank 1.2 V FMCP_LA_n[23] PIN_BU38 data n23 FMCP LA bank 1.2 V FMCP_LA_n[24] PIN_CA41 data n24 FMCP LA bank 1.2 V FMCP_LA_n[25] PIN_CF41 data n25 FMCP_LA_n[26] PIN_CL39 FMCP LA bank 1.2 V www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...
  • Page 45 LVDS input from the installed FMCP FMCP_GBTCLK_M2C_p[2] PIN_BB16 card to dedicated HCSL reference clock input pin Transmit pair p0 of High Speed Differential FMCP_DP_C2M_p[0] PIN_AU7 the FPGA transceiver www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...
  • Page 46 High Speed Differential FMCP_DP_C2M_p[9] PIN_BT7 the FPGA transceiver Transmit pair p10 High Speed Differential FMCP_DP_C2M_p[10] PIN_BL7 of the FPGA transceiver Transmit pair p11 High Speed Differential FMCP_DP_C2M_p[11] PIN_BG7 of the FPGA transceiver www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...
  • Page 47 High Speed Differential FMCP_DP_M2C_p[8] PIN_CB1 the FPGA transceiver Receiver pair p9 of High Speed Differential FMCP_DP_M2C_p[9] PIN_BV1 the FPGA transceiver Receiver pair p10 High Speed Differential FMCP_DP_M2C_p[10] PIN_BN1 of the FPGA transceiver www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...

  • Page 48: Usb To Uart

     *(1): Select by JP1, see section 2.2 : FMC+ HAB VCCIO Select Header . USB to UART One of the USB Type-C connector on Atum A5 board (J) is connected to three functions: USB blaster II interface, USB to UART for HPS and system MAX10. As shown in Figure Figure 2-19, the USB type C connector is connected to a 3-port USB HUB.
  • Page 49 UART to USB USB Blaster II CP2105 MAX 10 USB_UART_DP HPS_UART_RX_E HPS_UART_RX TXD_ECI HPS_UART_TX_E HPS_UART_TX USB_UART_DM RXD_ECI 1.8V to 3.3V Figure 2-20 Connections between the HPS of Atum A5 and FT232R Chip www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...
  • Page 50 UART interface. As shown Figure 2-21, the Atum A5 board provides several sensors to monitor the status of the board, such as FPGA temperature, board power monitor, and fan speed status. These interfaces are connected to the System MAX10 FPGA on the board.

  • Page 51: Ddr4 Sdram

    1.2-V POD PIN_A116 DDR4A_DQ2 Data [2] 1.2-V POD PIN_B130 DDR4A_DQ3 Data [3] 1.2-V POD PIN_B116 DDR4A_DQ4 Data [4] 1.2-V POD PIN_A130 DDR4A_DQ5 Data [5] 1.2-V POD PIN_B113 DDR4A_DQ6 Data [6] 1.2-V POD PIN_A128 www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...
  • Page 52 DIFFERENTIAL 1.2- DDR4A_DQS1 Data Strobe p[1] PIN_AG90 V POD DIFFERENTIAL 1.2-V DDR4A_DQS2 Data Strobe p[2] PIN_K95 DIFFERENTIAL 1.2-V DDR4A_DQS3 Data Strobe p[3] PIN_F95 DIFFERENTIAL 1.2- DDR4A_DQS_n0 Data Strobe n[0] PIN_A125 V POD www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...
  • Page 53 SSTL-12 PIN_Y114 Address [14]/ SSTL-12 DDR4A_A14 PIN_AB114 WE_n Address [15]/ DDR4A_A15 SSTL-12 PIN_AK107 CAS_n Address [16]/ DDR4A_A16 SSTL-12 PIN_AK104 RAS_n DDR4A_BA0 Bank Select [0] SSTL-12 PIN_AB108 DDR4A_BA1 Bank Select [1] SSTL-12 PIN_Y105 www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...
  • Page 54 1.2-V POD PIN_A82 DDR4B_DQ1 Data [1] 1.2-V POD PIN_B70 DDR4B_DQ2 Data [2] 1.2-V POD PIN_A85 DDR4B_DQ3 Data [3] 1.2-V POD PIN_A70 DDR4B_DQ4 Data [4] 1.2-V POD PIN_B82 DDR4B_DQ5 Data [5] 1.2-V POD PIN_B66 www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...
  • Page 55 V POD DIFFERENTIAL 1.2- DDR4B_DQS1 Data Strobe p[1] PIN_AG57 V POD DIFFERENTIAL 1.2-V DDR4B_DQS2 Data Strobe p[2] PIN_K55 DIFFERENTIAL 1.2-V DDR4B_DQS3 Data Strobe p[3] PIN_F55 DDR4B_DQS_n0 Data Strobe n[0] DIFFERENTIAL 1.2- PIN_B76 www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...
  • Page 56 Address [12] SSTL-12 PIN_AG79 DDR4B_A13 Address [13] SSTL-12 PIN_AG72 Address [14]/ SSTL-12 DDR4B_A14 PIN_AG75 WE_n Address [15]/ DDR4B_A15 SSTL-12 PIN_AG83 CAS_n Address [16]/ DDR4B_A16 SSTL-12 PIN_AC83 RAS_n DDR4B_BA0 Bank Select [0] SSTL-12 PIN_Y74 www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...

  • Page 57: Usb

    SMSC USB3320 (UTMI+ Low Pin Interface (ULPI) for HPS fabric. Both buses are connected to the external device through USB type-c connector. Figure 2-23 shows the connections of USB interface and FPGA. www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...
  • Page 58 Figure 2-23 Connections between the Atum A5 and USB interface USB 3.1 interface for HPS  This board implements USB3.1 interface through FPGA's GTS transceiver (HPS to FPGA) ,redriver IC and USB type-c connector. Table 2-26 lists the pin assignment of USB3.1 interface connected to the FPGA...

  • Page 59: Gigabit Ethernet

    The board supports Gigabit Ethernet transfer by an external Micrel KSZ9031RN PHY chip and HPS Ethernet MAC function. The KSZ9031RN chip with integrated 10/100/1000 Mbps Gigabit Ethernet transceiver also supports RGMII MAC interface. www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...
  • Page 60 For more information about the KSZ9031RN PHY chip and its datasheet, as well as the application notes, which are available on the manufacturer’s website. Figure 2-24 Connections between the HPS of Atum A5 and Ethernet PHY There are two LEDs, a green LED (LEDG) and a yellow LED (LEDY), which represent the status of the Ethernet PHY (KSZ9031RN).
  • Page 61 At the same time, the user can set the PHY address through SW26. For details, please see section 2.2 Ethernet PHY_ADR Setting Switch. Figure 2-25 shows the connections between the FPGA, 88E2110 PHY, and RJ-45 connector. www.terasic.com Apollo-Agilex SoM User Manual...
  • Page 62 SGMII receive data DIFFERENTIAL I/O ENET_88E2110_REFCLK_125M_p PIN_AT120 88E1512 reference clock ENET_88E2110_INT_n PIN_A20 Interrupt output pin 3.3V ENET_88E2110_MDC PIN_B14 Management data clock 3.3V reference ENET_88E2110_MDIO PIN_A14 Management data 3.3V ENET_88E2110_RESET_n PIN_B11 88E1512 reset pin 1.8V Apollo-Agilex SoM www.terasic.com User Manual June 24, 2024...

  • Page 63: 2X6 Gpio Header

    2.13 2x6 GPIO Header The Atum A5 board provides two 2x6 pin GPIO headers (HPS and FPGA for each) to expand the I/O of Agilex SoC FPGA (See Figure 2-26). Each header has numbers of the digital FPGA I/O user pins connected to the Agilex SoC FPGA, two 3.3V power pins and two ground pins.

  • Page 64: Qsfp+ Port

    Agilex SoC FPGA, and transform them to optical signals. A Low-Jitter programmable clock generator (Si5391B) will provide flexible clock for serial Figure 2-27 transceivers of the FPGA. shows the connections between the QSFP+ and Agilex SoC FPGA. www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...
  • Page 65 Transmitter data of channel 0 DIFFERENTIAL PIN_BE126 HIGH SPEED QSFP_TX_n[1] Transmitter data of channel 1 DIFFERENTIAL PIN_BC126 HIGH SPEED QSFP_TX_n[2] Transmitter data of channel 2 DIFFERENTIAL PIN_BA126 QSFP_TX_n[3] Transmitter data of channel 3 HIGH SPEED PIN_AW126 www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...
  • Page 66 Module Reset 3.3V PIN_B30 QSFP_SCL 2-wire serial interface clock 3.3V PIN_A30 QSFP_SDA 2-wire serial interface data 3.3V PIN_A35 QSFP_LP_MODE Low Power Mode 3.3V PIN_A33 QSFP_INTERRUPT_n Interrupt 3.3V PIN_A39 QSFP_MOD_PRS_n Module Present 3.3V PIN_B35 www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...

  • Page 67: Hdmi Output Port

    Agilex Pin Description I/O Standard Signal Name Number HDMI_TX_D0 Video Data bus HSSI DIFFERENTIAL I/O PIN_CD134 HDMI_TX_D1 Video Data bus HSSI DIFFERENTIAL I/O PIN_CD135 HDMI_TX_D2 Video Data bus HSSI DIFFERENTIAL I/O PIN_CG134 www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...
  • Page 68 Audio Reference Clock Input 3.3V PIN_BM118 Audio Left/Right Channel HDMI_LRCLK 3.3V PIN_BP112 Signal Input HDMI_SCLK I2S Audio Clock Input 3.3V PIN_BM112 FPGA_I2C_SCL FPGA I2C Clock 3.3V PIN_BR112 FPGA_I2C_SDA FPGA I2C Data 3.3V PIN_BM109 www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...

  • Page 69: Mipi Connector

    Figure 2-30 shows the connections between the FPGA and 22-pin MIPI connector. Table 3 25 shows the pin assignment of 22-pin MIPI connector. Figure 2-29 MIPI camera module connects to the board via cable www.terasic.com Apollo-Agilex SoM User Manual...
  • Page 70 PIN_K4 CAM_RZQ0 External reference ball for output 3.3V PIN_BR5 drive calibration Table 2-35 MIPI Connector 2 Pin Assignments, Schematic Signal Names, and Functions Schematic Description I/O Standard FPGA Pin Number Signal Name www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...
  • Page 71 MIPI Data 1 positive DPHY PIN_CA31 CAM2_D_n[0] MIPI Data 0 negative DPHY PIN_CF31 CAM2_D_n[1] MIPI Data 1 negative DPHY PIN_CC31 CAM2_I2C_SCL I2C clock 3.3V PIN_A8 CAM2_I2C_SDA I2C data 3.3V PIN_G1 CAM2_GPIO GPIO signal 3.3V PIN_J1 www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...

  • Page 72: Pci Express

    PCIe add-in card as shown in Figure 2-34, the longest length is up to 3 meters. These two associated devices are not included in the kit. To purchase the PCA3 card as well as the external cable, please refer to Terasic website pca3.terasic.com and PCIe_Cable.
  • Page 73 Figure 2-32 PCIe Cabling Adaptor(PCA) Gen 3 card Figure 2-33 PCIe External Cable Figure 2-34 PCIe Link Setup between Atum A5 and PC www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...
  • Page 74 PCIe Receiver data n2 I/O" PCIE_RX_n[3] PIN_BF133 HIGH SPEED DIFFERENTIAL PCIe Receiver data n3 I/O" PCIE_OB_REFCLK_p PIN_BC111 PCIe on-borad reference clock PCIE_REFCLK_p PIN_BB120 Motherboard reference clock PCIE_PERST_n PIN_BF107 3.3V Reset PCIE_WAKE_n PIN_D34 3.3V Wake signal Apollo-Agilex SoM www.terasic.com User Manual June 24, 2024...
  • Page 75 Apollo-Agilex SoM User Manual June 24, 2024...

  • Page 76: Chapter 3 Dashboard Gui

    To use the dashboard system, users need to install the USB to UART driver on the host first, so that user can establish a connection with the Atum A5 board. This section will describe how to install USB to UART driver on the windows OS host.

  • Page 77: Install Driver

    Connect the USB type-c connector of the board to the host PC USB port through USB type-c cable. Figure 3-2 Connect USB type-c cable to the board Connect power to the Atum A5 board. Figure 3-3 Connect power to the board Power on the Atum A5 board.

  • Page 78: Run Dashboard Gui

    Figure 3-5 he CP2105 in the Device Manager Run Dashboard GUI  Dashboard GUI software location Users can find it from the path: Tool\dashboard_gui\Dashboard.exe in the Atum A5 system CD and copy it to the host PC. Figure 3-6. It will describe the detail Execute the Dashboard.exe, a window will show as...
  • Page 79  GUI window. Click it to run the program (Start will change to Stop), it will show the Atum A5 board status. Users can press Stop button to stop the status data transmission and display. Reset Button: Press this button to clear the historical data shown in GUI, and ...
  • Page 80 Note that “CONF_DONE” stands for FPGA configure done status. There is no LED on Atum A5 board to display FPGA configure status. When this status is shown in green on the GUI, it means that FPGA configuration has been completed.
  • Page 81 Figure 3-8 FPGA Status section FPGA/Board/Board2/CorePower Temp.: The Dashboard GUI will real-time show  the fan speed, Atum A5 board ambient and FPGA temperature. Users can know the board temperature in time. The information will be refreshed per 1 second, and Figure 3-9.
  • Page 82 Figure 3-9 Temperature section Figure 3-10 Location of the board’s ambient temperature www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...
  • Page 83 Fan RPM: It displays the real-time speed of the fan on the Atum A5 board, as  Figure 3-11. shown in Figure 3-11 FAN RPM section 12V/ FPGA Core/ VCC1P2 Power monitor: It displays the real-time 12V /FPGA / ...
  • Page 84 Sampling Speed: It can change interval time that the Dashboard GUI sample the  board status. Users can adjust it to 1s/10s/1min/Full Speed (0.1s) to sample the board status, as shown in Figure 3-13 Figure 3-14. www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...
  • Page 85 Note that to active these functions, you will need to stop obtaining the board status (i.e. Don’t Press “Start” button) in the GUI. Detailed introductions of these functions are described in below. www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...
  • Page 86 GUI program window, click the Board Information to get the current software Figure 3-16. version and the Atum A5 board version, as shown in Note, user needs to stop the system monitor (press the “Stop” button on the Dashboard GUI), then you can run the Board Information.
  • Page 87 Export in the File page to save the board temperature, fan speed and voltage data in .csv format document, as shown in Figure 3-17 Figure 3-18. Figure 3-17 Export the log file Figure 3-18 Export the log file in .csv format www.terasic.com Apollo-Agilex SoM User Manual June 24, 2024...

  • Page 88: Install Driver For The Board

    Board Install the USB Blaster II Driver The Atum A5 board equipped with an USB-Blaster II circuit, it interfaces a USB port on a host computer to an Agilex SoC FPGA on the board. The USB-Blaster II circuit sends configuration data from the PC via the JTAG interface to the FPGA. To use USB-Blaster II circuit, user need to install the driver on your operation system.

  • Page 89: Chapter 5 Additional Information

    Here are the addresses where you can get help if you encounter problems:  Terasic Technologies No.80, Fenggong Rd., Hukou Township, Hsinchu County 303035. Taiwan Email: support@terasic.com Web: www.terasic.com Atum A5 Web: agilex-som.terasic.com  Revision History Date Version Changes 2024.06...

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