Terasic HAN Pilot Platform Demonstration Manual
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Terasic HAN Pilot Platform Demonstration Manual

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  • Page 2: Table Of Contents

    4.3 AXI bridges in Intel SoC FPGA ....................... 62 4.4 GHRD Project ............................63 4.5 Compile and Programming ........................64 4.6 Develop the C Code ..........................64 Chapter 5 PCI Express Design for Windows ............69 HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 3 7.1 Introduction ............................112 7.2 Use Linux BSP ............................112 7.3 Linux LXDE VNC Desktop BSP ......................113 7.4 Linux LXDE HDMI Desktop BSP ......................113 7.5 VNC Desktop OpenCL BSP ........................114 HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...

  • Page 4: Chapter 1 Introduction

     Pure use of HPS fabric resources (Chapter 3)  Use both FPGA and HPS fabric resources (Chapter 4) In addition, the PCIe example of HAN Pilot Platform will be described separately in one chapter (Chapter 5) because of its high content.

  • Page 5: Examples For Fpga

    DDR4, PCIe, HDMI and USB Controller. All the associated files can be found in the directory \Demonstrations\FPGA of HAN Pilot Platform system CD. The HAN Pilot Platform has a default configuration bit-stream pre-programmed, which demonstrates some of the basic features on board. This demo used LED,7-Segments, Switch, HDMI transmitter display and fan control.
  • Page 6 Demonstration Setup 1. Make sure Quartus Prime is installed on the host PC. 2. Connect HAN Pilot Platform to the host PC via USB cable. Install the USB-Blaster II driver if necessary. 3. Connect the HDMI TX to displayer via HDMI cable.

  • Page 7: Nios Ii Control For Programmable Pll/ Temperature/ Power/ 9-Axis

    Qsys System Interconnect Fabric through PIO controllers. The Nios II program toggles the PIO controller to implement the I2C protocol. The Nios II program is running in the on-chip memory. HAN Pilot Platform www.terasic.com Demonstration Manual...
  • Page 8 With the menu, users can perform the test for the temperature sensor, power monitor, external programmable PLL and 9-axis outputs. Note, pressing ‘ENTER’ should be followed with the choice number. Figure 2-5 Menu of Demo Program HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 9 In the external PLL programming test, the program will program the PLL first, and subsequently will use TERASIC QSYS custom CLOCK_COUNTER IP to count the clock count in a specified period to check whether the output frequency is changed as configured. For CDCM6208 programming, the program can control the CDCM6208 to configure the output frequency of SATA/PCIE/DDR4A/DDR4B/DDR4H REFCLK according to your choice.
  • Page 10 Figure 2-7 Power Monitor Demo 9. For 9-axis test, please input key ‘2’ and press ‘Enter’ in the nios-terminal, the Nios II console will display the values of 9-axis as shown in Figure 2-8. HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 11 Figure 2-9 TXCA Demo 11. For programmable PLL TXCB test, please input key ‘4’ and press ‘Enter’ in the nios-terminal first, then select the desired output frequency of DP/USB/FMC REFCLK, as shown in Figure HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 12 12. For programmable PLL CDCM6208 test, please input key ‘5’ and press ‘Enter’ in the nios-terminal first, then select the desired output frequency of SATA/ PCIE/ DDR4A/ DDR4B/ DDR4H REFCLK, as shown in Figure 2-11. HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...

  • Page 13: Nios Ddr4 Sdram Test

    Nios II processor. Nios II processor is used to perform memory test. The Nios II program is running in the On-Chip Memory. A PIO Controller is used to monitor buttons status which is used to trigger starting memory testing. HAN Pilot Platform www.terasic.com Demonstration Manual...
  • Page 14 ‘Clean’ from the ‘Project’ menu of Nios II Eclipse.  Demonstration Batch File Demo Batch File Folder: NIOS_DDR4 \demo_batch The demo batch file includes following files:  Batch File for USB-Blaster II: test.bat, test.sh  FPGA Configure File: NIOS_DDR4.sof HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...

  • Page 15: Rtl Ddr4 Sdram Test

    2.4 RTL DDR4 SDRAM Test This demonstration performs a memory test function on the one DDR4 SO-DIMM (DDR4A) and one DDR4 Component (DDR4B) on the HAN Pilot Platform. The memory size of DDR4 SO-DIMM is 4GB and DDR4 Component is 1GB.
  • Page 16  Demonstration Setup 1. Make sure Quartus Prime is installed on the host PC. 2. Connect HAN Pilot Platform to the host PC via USB cable. Install the USB-Blaster II driver if necessary. 3. Set MSEL[2:0] to 010. 4. Power on the HAN Pilot Platform.

  • Page 17: Usb Type-C Displayport Alternate Mode

    DisplayPort IP is generated by VIP Test Pattern Generator II IP and VIP Clocked Video Output II IP. In the system, a Nios II processor is used to control the DisplayPort IP. The Nios II Processor is running on on-chip memory with 100Mhz. HAN Pilot Platform www.terasic.com Demonstration Manual...
  • Page 18 Note: Quartus 17.0 Standard is used for these demonstration design. Use Quartus 18.0 could make malfunction.  Demonstration Setup and Instructions 1. Make sure Quartus Prime is installed on your PC. HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...

  • Page 19: Usb Type-C Fx3 Loopback

    This demonstration illustrates how the FX3 is working with the FPGA for USB3.0/USB2.0 data bulk in/out (data loop transmission). There is a USB type-C connector onto HAN Pilot Platform, a type-C cable is reversible for plugging in the USB type-C connector. This demonstration also implements the auto-switching mechanism for a type-C cable plugging in on either side.
  • Page 20 Figure 2-16 Block diagram of the USBC FX3 design  Demonstration Setup  Hardware Setting Up, as shown in Figure 2-17. Figure 2-17 USBC FX3 Demo Hardware Setting Up  Design Tools  Quartus Prime 18.0 Standard Edition HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 21  Demonstration Setup  Connect the HAN Pilot Platform USB Blaster II connector (J20) to the host PC with a USB cable and install the USB-Blaster II driver if necessary.  Use a Type-C cable to connect the HAN Pilot Platform and a PC (with a Type-C connector).
  • Page 22 Table 2-3 The functional keys of the HAN Pilot Platform USBC_FX3 demonstration Name Description LED0 lights off indicates Type-C Cable two sides plugged with same directions. LED0 LED0 lights up indicates Type-C Cable two sides plugged with reverse directions. LED1 It lights up when the USB signal is detected.

  • Page 23: Hdmi Tx And Rx In 4K Resolution

    2-20, user can connect an HDMI video player to the input video and audio data to HDMI RX port of the HAN Pilot Platform. After the HDMI video data is received in the FPGA, it will be instantly transferred to the HDMI TX port.
  • Page 24 EDID and the HDMI IP in this demo. The HDMI Video player is then connected to the HDMI RX port of the HAN Pilot Platform. When the RX instance in the FPGA receives a video source from the external video generator, the video and audio data then go through a loopback FIFO before it is transmitted to the TX instance.
  • Page 25 FPGA Configure File: a10_hdmi2_demo.sof  Nios II Program: HDMI_RX_TX.elf  Hardware Requirement  A PC  An HDMI monitor capable of displaying 4K/60P  An HDMI video player capable of outputting 4K/60P resolution HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 26 Figure 2-23 Connection setup of the HDMI TX monitor and HAN Pilot Platform 4. Connect the USB Blaster II port on the HAN Pilot Platform to the computer using the USB cable (Do not connect the HDMI video player at this time).

  • Page 27: Hdmi Tx In 4K Resolution

    HDMI TX IP. The resolution of the generated pattern can be 4K or Full HD (1080). User can switch the output resolution instantly through the Switch on the HAN Pilot Platform. The HDMI TX IP is identical to section 2.7. HAN Pilot Platform www.terasic.com Demonstration Manual...
  • Page 28 2. Connect a HDMI monitor to the HAN Pilot Platform as shown in Figure 2-23. 3. Connect the USB Blaster II port on the HAN Pilot Platform to the computer using the USB cable (do not connect the HDMI video player at this time). 4. Set MSEL[2:0] to 010.

  • Page 29: Low Latency Ethernet 10G Mac Demo

    Ethernet 10G MAC Intel Arria 10 FPGA IP Design Example User Guide. The LL (Low Latency) 10GbE IP is used in the example design. This example executes the external loopback test through HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 30 File monitor_conf.tcl show_stats.tcl Quartus Quartus Prime 18.0.0 Build 614 Standard Edition Version  Demonstration Setup Here is the procedure to setup the demonstration. A SFP+ loopback fixture is required for this HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 31 1. Insert a SFP+ loopback fixture into the SFP+-A port on the HAN Pilot Platform as shown in Figure 2-28. Figure 2-28 SFP+-A loopback on the HAN Pilot Platform 2. Connect the host PC to the FPGA board using a Mini-USB cable. Please make sure the USB-Blaster II driver is installed on the host PC.
  • Page 32 11. Type “source show_stats.tcl” to checks the number of good and bad packets received. as shown Figure 2-32. 12. Wait 6 minutes to complete loopback task, then re-type “source monitor_conf.tcl” to see “0xffff2000” good packets. Figure 2-29 Launch the System Console for Ethernet 10GBASE-R Demo HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 33 Figure 2-30 Ethernet 10BASE-R test message for gen_conf.tcl Figure 2-31 Ethernet 10BASE-R test message for monitor_conf.tcl HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...

  • Page 34: Socket Server

    Figure 2-32 Ethernet 10BASE-R test message for show_stats.tcl 2.10 Socket Server The Arria 10 device on the HAN Pilot Platform consists of built-in serializer/reserialize (SERDES) circuitry for high-speed LVDS interfaces to support Gigabit Ethernet. Ethernet has been the dominant networking protocol providing a simple, cost-effective option for backbone and server connectivity.
  • Page 35 HAN Pilot Platform with a Simple Socket Server. The Simple Socket Server continues to listen for commands on a TCP/IP port and operates the HAN Pilot Platform according to the commands from the telnet client. NicheStack TCP/IP stack uses the MicroC/OS-II RTOS multithreaded environment to provide immediate access to a stack for Ethernet connectivity for the Nios II processor.
  • Page 36 100 MHz and the desired MDC clock frequency is 2.5 MHz, a host clock divisor of 40 should be used. Once the Triple-Speed Ethernet IP configuration has been set and necessary hardware connections has been made click on ‘Generate’ to build the interconnect HAN Pilot Platform www.terasic.com Demonstration Manual...
  • Page 37 Nios II processor and through the Simple Socket Server it will send server command to the HAN Pilot Platform. The packet sent contains LED command which is extracted and dispatched to the LED command queue for processing by the LED management tasks.
  • Page 38 2. Use USB Cable to connect PC and the FPGA board and install USB Blaster II driver if necessary. 3. Connect the ethernet to Router or network switch with DHCP. 4. Set MSEL[2:0] to 010. HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 39 8. To establish connection, start the telnet client session by executing open_telnet.bat file and include the IP address assigned by the DHCP server-provided IP along with the port number as shown below in Figure 2-39. HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...

  • Page 40: Auto Fan Speed Control

    9. From the Simple Socket Server Menu, enter the commands in the telnet session. Entering a number from zero through one followed by a return causes the corresponding the LEDs (LED0-LED1) to toggle on or off on the HAN Pilot Platform. 2.11 Auto Fan Speed Control This demonstration shows you how to adjust the fan rotation speed according to the FPGA chip temperature value.
  • Page 41 The one is an I2C controller (FAN_TEMP_I2C), which can be used to read the temperature value of the HAN Pilot Platform Temperature Sensor IC (TMP441) and to set the Fan Controller IC (MAX6650) register for controlling the fan rotation speed. Both the Temperature Sensor and the Fan Controller use the same I2C bus.
  • Page 42 SW1=0, display FPGA temperature value. The following are the descriptions of the platforms’ set up, as well as the test steps.  AutoFan RTL Demonstration Setup  Hardware Setting Up As shown in Figure 2-42: HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 43  Demonstration Setup  Connect the HAN Pilot Platform USB Blaster II port (J20) to the host PC with a USB cable and install the USB-Blaster II driver if necessary.  Plug the 12V adapter to HAN Pilot Platform Board.
  • Page 44 HEX[1:0] Display two decimal numbers When the Fan rotation speed is abnormal (ex, fan doesn’t rotate), LED0 lights up LED0 LED1 When the FPGA temperature value is greater than 50ºC, LED1 lights up HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...

  • Page 45: Examples For Hps Soc

    These examples demonstrate major features connected to HPS interface on HAN Pilot Platform such as users LED/KEY, Network Communication. All the associated files can be found in the directory Demonstrations/SOC of the HAN Pilot Platform System CD. Please refer to Chapter 5 "Running Linux on the HAN Pilot Platform" from the HAN Pilot Platform Getting Start Guide.
  • Page 46 IO pin in the associated GPIO controller and so on. The value "1" in the register bit indicates the input state is high, and the value "0" indicates the input state is low. HAN Pilot Platform www.terasic.com Demonstration Manual...
  • Page 47 "socal/alt_gpio.h"  LED and KEY Control Figure 3-4 shows the HPS users LED and KEY pin assignment for the HAN Pilot Platform. The LED is connected to GPIO1_IO1 and the KEY is connected to GPIO1_IO4. HAN Pilot Platform www.terasic.com...
  • Page 48 ( virtual_base + ALT_GPIO_SWPORTA_DR_OFST ), BIT_LED ); The following statement is used to read the content of gpio_ext_porta register. The bit mask is used to check the status of the key. alt_read_word( virtual_base + ALT_GPIO_EXT_PORTA_OFST ); HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...

  • Page 49: Setup Usb Wi-Fi Dongle

    Execute command: ./hps_gpio  Demonstration Setup 1. Connect a USB cable to the USB-to-UART connector (J27) on the HAN Pilot Platform and the host PC. 2. Copy the executable file "hps_gpio" into the microSD card under the "/home/root" folder in Linux.
  • Page 50  Wi-Fi Setup Procedure 1. Connect a USB cable to the USB-to-UART connector (J27) on the HAN Pilot Platform and the host PC. 2. Connect the USB Wi-Fi Dongle into the USB port on the HAN Pilot Platform with USB Transfer Cable.
  • Page 51 Figure 3-12. 11. Make sure Wi-Fi AP is connected to the internet. Type "ping -c 4 www.terasic.com" in the UART terminal to check internet connection status. If 0% packet loss is reported, it means the connection is good, as shown in Figure 3-13.

  • Page 52: Hps Gpio Header

    Figure 3-13 Type "ping -c 4 www.terasic.com" This demonstration shows how to use the system call with built-in GPIO driver to implement HPS GPIO Header’s loopback. The built-in GPIO driver is included the HAN Pilot Platform LXDE VNC Desktop BSP.
  • Page 53 The parameter “gpio” is the gpio port that you want to read. All the functions are implemented in the c code file, you can get more details from the c code file. HAN Pilot Platform www.terasic.com...
  • Page 54 Figure 3-15 loopback implemented in c code  Demonstration Source Code  Build tool: SoC EDS V18.0  Project directory: \Demonstration\SoC\hps_gpio_loopback  Binary file: hps_gpio_loopback  Build command: make ('make clean' to remove all temporal files) HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 55 Figure 3-16 GPIO Header Pin location 2. Connect a USB cable to the USB-to-UART connector (J27) on the HAN Pilot Platform and the host PC. 3. Copy the executable file "hps_gpo_loopback" into the microSD card under the "/home/root"...

  • Page 56: Network Socket

    LAN, or across the Internet, but they can also be used for interposes communication on a single computer. Figure 3-18 Communicate on a network via a socket HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 57 The steps involved in establishing a socket on the server side are as follows:  Create a socket with the socket() system call  Bind the socket to an address using the bind() system call. For a server socket on the HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 58 The major function of the socket client program is to create a connection based on given hostname (or IP address) and host port. When a connection is established, it will show “Please enter the message:” message on console terminal to ask users to input a message. After get user’s input HAN Pilot Platform www.terasic.com Demonstration Manual...
  • Page 59 Linux running on Linux PC. The project under windows folder is designed for SoC EDS Shell running on Windows PC. Each platform subfolder contains socket_client and socket_server project folders. HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 60 Windows PC. 1. Connect the HAN Pilot Platform to Network via Ethernet port (J25). 2. Connect a USB cable to the USB-to-UART connector (J27) on the HAN Pilot Platform and the host Windows PC. 3. Copy the executable file “socket_server” into the microSD card under the "/home/root" folder in Linux.
  • Page 61 3-25. At the same time, the socket server program will dump the received message at which point it is terminated as shown in Figure 3-26. Figure 3-25 Send Message in Client Program Figure 3-26 Server dumps received message HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...

  • Page 62: Examples For Using Both Hps Soc And Fpga

    Skill to Create a Linux Boot SD-Card for HAN Pilot Platform with a given image file  Skill to boot Linux from SD-Card on HAN Pilot Platform Skill to copy files into Linux file system on HAN Pilot Platform Basic Linux command operation skill...

  • Page 63: Axi Bridges In Intel Soc Fpga

    The clock domain for each interconnect is noted in parentheses. Figure 4-1 AXI Bridge Block Diagram The HPS-to-FPGA bridge is mastered by the level 3 (L3) main switch and the lightweight HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...

  • Page 64: Ghrd Project

    HPS-to-FPGA bridge. This Demo introduces to users how to use the HPS/ARM to communicate with FPGA. This project includes GHRD project for the HAN Pilot Platform one ARM C Project which demonstrates how HPS/ARM program controls the LEDs connected to FPGA.

  • Page 65: Compile And Programming

    When the compilation process is completed successfully, a10s.sof is generated in the a10s_ghrd\output_files folder. Users can use this file to configure FPGA by Quartus Programming through the HAN Pilot Platform on-board USB-Blaster II. This section introduces how to design an ARM C program to control the led_pio PIO controller.
  • Page 66 The virtual address of led_pio is represented by a void pointer variable h2p_lw_led_addr. Application program can directly use the pointer variable to access the registers in the controller of LED_PIO. HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 67 PIO Core. For led control, we just need to write output value to the offset 0 register. Because the led on HAN Pilot Platform is low active, writing a value 0x00000003 to the offset 0 register will turn off the two LEDs. Writing a value 0x00000000 to the offset 0 register will turn on the two LEDs.
  • Page 68 SoC EDS. In the Makefile, ARM-linux cross-compile also be specified. Figure 4-8 Makefile content To compile the project, type “make” in the command shell as shown in 4-9. Then, type “ls” Figure to check the generated ARM execution file “hps_fpga_led”. HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 69  Execute the Demo To execute the demo, please boot the Linux from the SD-card in HAN Pilot Platform. Copy the execution file “hps_fpga_led” to the Linux directory, and type “chmod +x hps_fpga_led” to add execution attribute to the execute file. Then, type “./ hps_fpga_led” to launch the ARM program.

  • Page 70: Pci Express Design For Windows

    FPGA System and PC System. The FPGA System is developed based on Arria 10 Hard IP for PCI Express with Avalon-MM DMA. The application software on the PC side is developed by Terasic based on Intel’s PCIe kernel mode driver. Figure 5-1 Infrastructure of PCI Express System HAN Pilot Platform www.terasic.com...

  • Page 71: Pc Pci Express Software Sdk

    The PCIe library module TERASIC_PCIE_AVMM.dll provides DMA and direct I/O access for user application program to communicate with FPGA. Users can develop their applications based on this DLL. The altera_pcie_win_driver.sys kernel driver is provided by Altera. Figure 5-2 PCI Express Software Stack HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 72 WdfCoinstaller01011.dll To install the PCI Express driver, please execute the steps below: 1. Make sure the HAN Pilot Platform and the PC are both powered off. 2. Set MSEL[2:0] to 010. 3. Plug the PCIe adapter card into the PCIe slot on the PC motherboard. Use the PCIe cable to...
  • Page 73 9. In the How do you want to search for driver software dialog, click Browse my computer for driver software item, as shown in Figure 5-5. Figure 5-5 Dialog of Browse my computer for driver software HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 74 Figure 5-6 Browse for driver software on your computer 11. When the Windows Security dialog appears, as shown Figure 5-7, click the Install button. Figure 5-7 Click Install in the dialog of Windows Security HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 75 13. Once the driver is successfully installed, users can see the Altera PCI API Driver under the device manager window, as shown in Figure 5-9. Figure 5-9 Altera PCI API Driver in Device Manager HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...

  • Page 76: Pci Express Library Api

    Specify the matched card index, a zero based index, based on the matched vendor ID and device ID. Return Value: Return a handle to presents specified PCIe card. A positive value is return if the PCIe card is opened HAN Pilot Platform www.terasic.com Demonstration Manual...
  • Page 77 A buffer to retrieve the 32-bit data. Return Value: Return true if read data is successful; otherwise false is returned.  PCIE_Write32 Function: Write a 32-bit data to the FPGA Board. Prototype: bool PCIE_Write32( PCIE_HANDLE hPCIE, HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 78 Return Value: Return true if read data is successful; otherwise false is returned.  PCIE_Write8 Function: Write an 8-bit data to the FPGA Board. Prototype: bool PCIE_Write8( PCIE_HANDLE hPCIE, PCIE_BAR PcieBar, HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 79 Specify the byte number of data retrieved from FPGA. Return Value: Return true if read data is successful; otherwise false is returned.  PCIE_DmaWrite Function: Write data to the memory-mapped memory of FPGA board in DMA. Prototype: bool PCIE_DmaWrite( HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...

  • Page 80: Pcie Reference Design - Fundamental

    The application reference design shows how to implement fundamental control and data transfer in DMA. In the design, basic I/O is used to control the BUTTON and LED on the FPGA board. High-speed data transfer is performed by DMA. HAN Pilot Platform www.terasic.com Demonstration Manual...
  • Page 81 PCIe driver necessary. driver located folder: CDROM\Demonstration\PCIe_SW_KIT\Windows\PCIe_Driver. 5. Restart Windows 6. Make sure the Windows has detected the FPGA Board by checking the Windows Control panel as shown in Figure 5-11. HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 82 8. Type 0 followed by a ENTER key to select Led Control item, then input 15 (hex 0x0f) will make all led on as shown in Figure 5-13. If input 0 (hex 0x00), all led will be turn off. HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 83 Figure 5-14 Screenshot of Button Status Report 10. Type 2 followed by an ENTER key to select DMA Testing item. The DMA test result will be report as shown in Figure 5-15. HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 84 LED and monitor the Button Status, and the On-Chip memory is used for performing DMA testing. The PIO controllers and the On-Chip memory are connected to the PCI Express Hard IP controller through the Memory-Mapped Interface. HAN Pilot Platform www.terasic.com Demonstration Manual...
  • Page 85 The main program PCIE_FUNDAMENTAL.cpp includes the header file "PCIE.h" and defines the controller address according to the FPGA design, as shown in Figure 5-17. Figure 5-17 Header file "PCIE.h" HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...

  • Page 86: Pcie Reference Design - Ddr4

    The demo file is located in the batch folder: CDROM\ Demonstrations\PCIe_DDR4\demo_batch The folder includes following files:  FPGA Configuration File: PCIe_DDR4.sof  Download Batch file: test.bat  Windows Application Software folder: windows_app, includes  PCIE_DDR4.exe HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 87 5-20. Gen3 link speed and x8 link width are expected. 10. Type 3 followed by an ENTER key to select DMA On-Chip Memory Test item. The DMA write and read test result will be report as shown in Figure 5-21. HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 88 Figure 5-19 Screenshot of Program Menu Figure 5-20 Screenshot of Link Info Figure 5-21 Screenshot of On-Chip Memory DMA Test Result HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 89 12. Type 5 followed by an ENTER key to select DMA DDR4-B Memory Test item. The DMA write and read test result will be report as shown in Figure 5-23. Figure 5-23 Screenshot of DDR4-B SOSIMM Memory DAM Test Result HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 90 Windows Based Application Software Design The application software project is built by Visual C++ 2012. The project includes the following major files: NAME Description PCIE_FUNDAMENTAL.cpp Main program PCIE.c Implement dynamically load for TERAISC_PCIE_AVMM.DLL HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 91 The button status query is implemented by calling the PCIE_Read32 API, as shown below: The memory-mapped memory read and write test is implemented by PCIE_DmaWrite and PCIE_DmaRead API, as shown below: The PCIe link information is implemented by PCIE_ConfigRead32 API, as shown below: HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 92 HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...

  • Page 93: Chapter 6 Pci Express Design For Linux

    FPGA System and PC System. The FPGA System is developed based on Arria 10 Hard IP for PCI Express with Avalon-MM DMA. The application software on the PC side is developed by Terasic based on Intel’s PCIe kernel mode driver. Figure 6-1 Infrastructure of PCI Express System HAN Pilot Platform www.terasic.com...

  • Page 94: Pc Pci Express Software Sdk

    PCIe library module terasic_pcie_qys.so provides DMA and direct I/O access for user application program to communicate with FPGA. Users can develop their applications based on this .so library file. The altera_pcie.ko kernel driver is provided by Altera. Figure 6-2 PCI Express Software Stack HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 95 To compile and install the PCI Express driver, please execute the steps below: 1. Make sure the HAN Pilot Platform and the PC are both powered off. 2. Set MSEL[2:0] to 010. 3. Plug the PCIe adapter card into the PCIe slot on the PC motherboard. Use the PCIe cable to...
  • Page 96 5. Call the library API to implement the desired application. Users can easily communicate with the FPGA through the PCIe bus through the terasic_pcie_qsys.so API. The details of API are described below. HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...

  • Page 97: Pci Express Library Api

     PCIE_Close Function: Close a handle associated to the PCIe card. Prototype: void PCIE_Close( PCIE_HANDLE hPCIE); Parameters: hPCIE: A PCIe handle return by PCIE_Open function. Return Value: None.  PCIE_Read32 Function: HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 98 Specify a 32-bit data which will be written to FPGA board. Return Value: Return true if write data is successful; otherwise false is returned.  PCIE_Read8 Function: Read an 8-bit data from the FPGA board. HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 99 Return true if write data is successful; otherwise false is returned.  PCIE_DmaRead Function: Read data from the memory-mapped memory of FPGA board in DMA. Maximal read size is (4GB-1) bytes. HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 100 A pointer to a memory buffer to store the data which will be written to FPGA. dwDataSize: Specify the byte number of data which will be written to FPGA. Return Value: Return true if write data is successful; otherwise false is returned.  PCIE_ConfigRead32 HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...

  • Page 101: Pcie Reference Design - Fundamental

    Linux Application Software folder: linux_app, includes  PCIE_FUNDAMENTAL  terasic_pcie_qsys.so  Demonstration Setup 1. Set MSEL[2:0] to 010. 2. Install the FPGA board on your PC as shown in Figure 6-5. HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 102 Figure 6-6. Figure 6-6 Linux has detected the FPGA Board 9. Go to linux_app folder, execute PCIE_FUNDAMENTAL. A menu will appear as shown in Figure 6-7. HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 103 11. Type 1 followed by an ENTER key to select Button Status Read item. The button status will be report as shown in Figure 6-9. Figure 6-9 Screenshot of Button Status Report HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 104 LED and monitor the Button Status, and the On-Chip memory is used for performing DMA testing. The PIO controllers and the On-Chip memory are connected to the PCI Express Hard IP controller through the Memory-Mapped Interface. HAN Pilot Platform www.terasic.com Demonstration Manual...
  • Page 105 FPGA design, as shown in Figure 6-12. Figure 6-12 Header file "PCIE.h" The base address of BUTTON and LED controllers are 0x4000010 and 0x4000020 based on HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...

  • Page 106: Pcie Reference Design - Ddr4

    The demo file is located in the batch folder: CDROM\ Demonstrations\PCIe_DDR4\demo_batch The folder includes following files:  FPGA Configuration File: PCIe_DDR4.sof  Download Batch file: test.sh  Linux Application Software folder: linux_app, includes  PCIE_DDR4 HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 107 7. Restart Linux. 8. Install PCIe driver. 9. Make sure the Linux has detected the FPGA Board. 10. Go to linux_app folder, execute PCIE_DDR4. A menu will appear as shown in Figure 6-14. HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 108 Screenshot of Link Info 12. Type 3 followed by an ENTER key to select DMA On-Chip Memory Test item. The DMA write and read test result will be report as shown in Figure 6-16. HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 109 13. Type 4 followed by an ENTER key to select DMA DDR4-A SODIMM Memory Test item. The DMA write and read test result will be report as shown in Figure 6-17. Figure 6-17 Screenshot of DDR4-A SOSIMM Memory DAM Test Result HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 110 LED and monitor the Button Status, and the On-Chip memory is used for performing DMA testing. The PIO controllers and the On-Chip memory are connected to the PCI Express Hard IP controller through the Memory-Mapped Interface. HAN Pilot Platform www.terasic.com Demonstration Manual...
  • Page 111 The above definition is the same as those in PCIe Fundamental demo. Before accessing the FPGA through PCI Express, the application first calls PCIE_Load to dynamically load the TERASIC_PCIE_AVMM.DLL. Then, it call PCIE_Open to open the PCI HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 112 The button status query is implemented by calling the PCIE_Read32 API, as shown below: The memory-mapped memory read and write test is implemented by PCIE_DmaWrite and PCIE_DmaRead API, as shown below: The PCIe link information is implemented by PCIE_ConfigRead32 API, as shown below: HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...

  • Page 113: Chapter 7 Linux Bsp

    These Linux BSP can be downloaded for free from the Terasic Website: http:// HAN Pilot Platform.terasic.com/cd This section describes the procedure to boot Linux on HAN Pilot Platform. For more details, refer to chapter 5 of HAN Pilot Platform_Getting_Started_Guide.pdf in the System CD.

  • Page 114: Linux Lxde Vnc Desktop Bsp

     For HDMI mode:  Connect a HDMI monitor, an USB keyboard, and a USB mouse to the HAN Pilot Platform with USB Hub  Power on HAN Pilot Platform  The LXDE Desktop will appear on the HDMI monitor This is a VNC mode Linux BSP.

  • Page 115: Vnc Desktop Opencl Bsp

    Open Computing Language (OpenCL™) allows a user to abstract away the traditional hardware FPGA development flow for a much faster and higher level software development flow. For more details, please refer to HAN Pilot Platform_OpenCL.pdf in the HAN Pilot Platform System CD. Table 7-3 lists the OpenCL BSP component reference and the related information.
  • Page 116 OpenCL Example Codes Source: https://github.com/terasic/linux-socfpga/tree/socfpga-3.10 Branch: socfpga-3.10 Linux Kernel Source Under above location: Configure File: Reserved HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...
  • Page 117 9F, No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, Taiwan 300-70 Email : support@terasic.com Web : www.terasic.com Date Version Changes 2018.04.16 First publication 2019.07.07 v1.1 Modify figures which are show as DE10-Advanced. 2019.09.06 v1.2 Modify default code section HAN Pilot Platform www.terasic.com Demonstration Manual September 6, 2019...

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