1. Manuals
  2. Brands
  3. Terasic Manuals
  4. Microcontrollers
  5. DE25-Standard
  6. User manual

Terasic DE25-Standard User Manual

Hide thumbs Also See for DE25-Standard:
Table of Contents

Advertisement

Quick Links

Download this manual

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the DE25-Standard and is the answer not in the manual?

Questions and answers

Related Manuals for Terasic DE25-Standard

Summary of Contents for Terasic DE25-Standard

  • Page 2: Table Of Contents

    Chapter 3 Using the DE25-Standard Board ..........11 3.1 Settings of FPGA Configuration Mode ..................11 3.2 Configuration of Agilex 5 SoC FPGA on DE25-Standard ............12 3.3 Board Status Elements ......................17 3.4 Board Reset Elements ....................... 18 3.5 Clock Circuitry ......................... 19 3.6 USB Type-C Connector ......................
  • Page 3 Dashboard GUI ................54 4.1 Setup for the Dashboard GUI ....................54 4.2 Run Dashboard GUI ......................... 56 Chapter 5 Appendix ..................64 5.1 Revision History ........................64 5.2 Copyright Statement ......................... 64 DE25-Standard www.terasic.com User Manual June 7, 2024...

  • Page 4: De25-Standard Development Kit

    Ethernet networking, MIPI interface and much more that promise many exciting applications. The DE25-Standard Development Kit contains all the tools needed to use the board in conjunction with a computer that runs the Microsoft Windows 10.

  • Page 5: Package Contents

    Fan (Installed) DE25-Standard System CD The DE25-Standard System CD contains all the documents and supporting materials associated with DE25-Standard, including the user manual, system builder, reference designs, and device datasheets. Users can download this system CD from the link: http://DE25-standard.terasic.com/cd/.

  • Page 6: Getting Help

    Getting Help Here are the addresses where you can get help if you encounter any problems: Terasic Technologies No.80, Fenggong Rd., Hukou Township, Hsinchu County, 303035 Taiwan Email: support@terasic.com Tel.: +886-3-575-0880 Website: DE25-standard.terasic.com DE25-Standard www.terasic.com User Manual June 7, 2024...

  • Page 7: Introduction Of The De25-Standard Board

    Layout and Components Figure 2-1 shows a photograph of the board. It depicts the layout of the board and indicates the location of the connectors and key components. Figure 2-1 DE25-Standard development board (top view) DE25-Standard www.terasic.com User Manual June 7, 2024...

  • Page 8: Block Diagram Of The De25-Standard Board

    The DE25-Standard board has many features that allow users to implement a wide range of designed circuits, from simple circuits to various multimedia projects. The following hardware is provided on the board: FPGA Agilex 5 SoC FPGA : A5ED013BB32AE4S (130K LEs) ASx4 128Mbits QSPI Flash USB-Blaster II onboard for programming;...

  • Page 9: Memory Device

    Figure 2-2 Block diagram of DE25-Standard Detailed information about Figure 2-2 are listed below. FPGA Device Agilex™ 5 SoC FPGA : A5ED013BB32AE4S ARM Cortex Processor with 2xA55 and 2xA76 138K programmable logic elements 8.42 Mbits embedded memory 376 18-bit x 19-bit multipliers MIPI D-PHY v2.5...
  • Page 10 Switches, Buttons, and Indicators 5 user Keys (FPGA x4, HPS x1) 10 user switches (FPGA x10) 11 user LEDs (FPGA x10, HPS x 1) 1 HPS reset buttons (HPS_Cold_RESET_n) Six 7-segment displays Sensors G-Sensor on HPS DE25-Standard www.terasic.com User Manual June 7, 2024...
  • Page 11 Power 12V DC input DE25-Standard www.terasic.com User Manual June 7, 2024...

  • Page 12: Using The De25-Standard Board

    This chapter provides an instruction to use the board and describes the peripherals. Settings of FPGA Configuration Mode When the DE25-Standard board is powered on, the FPGA can be configured from QSPI FLASH or HPS. The MSEL[2:0] pins are used to select the configuration scheme. It is implemented as a 4-pin...

  • Page 13: Configuration Of Agilex 5 Soc Fpga On De25-Standard

    The information is retained within QSPI Flash even if the DE25-Standard board is turned off. When the board is powered on, the configuration data in the QSPI Flash device is automatically loaded into the Agilex 5 SoC FPGA.
  • Page 14 The following shows how the FPGA is programmed in JTAG mode step by step. 1. Open the Quartus Programmer tool, make sure the USB blaster II (“Agilex 7 FPGA Starter Kitp[USB-x]”)is found in “Hardware Setup..” tab. DE25-Standard www.terasic.com User Manual...
  • Page 15 Figure 3-4 USB blaster II is found in Programmer 2. Open the Programmer and click “Auto Detect”, as circled in Figure 3-5 Figure 3-5 Detect FPGA device in JTAG mode DE25-Standard www.terasic.com User Manual June 7, 2024...
  • Page 16 4. Right click on the FPGA device and open the .sof file to be programmed, as highlighted in Figure 3-7. Figure 3-7 Open the .sof file to be programmed into the FPGA device DE25-Standard www.terasic.com User Manual June 7, 2024...
  • Page 17 Figure 3-8 Select the .sof file to be programmed into the FPGA device 6. Click “Program/Configure” checkbox and then click “Start” button to download the .sof file Figure 3-9. into the FPGA device, as shown in Figure 3-9 Program .sof file into the FPGA device DE25-Standard www.terasic.com User Manual June 7, 2024...

  • Page 18: Board Status Elements

    In addition to the 10 LEDs that FPGA device can control, there are 5 indicators which can indicate the board status (See Figure 3-10), please refer the details in Table 3-3. Figure 3-10 LED Indicators on DE25-Standard LED Indicators Table 3-3 Board Reference LED Name Description Illuminates when 12V power is active.

  • Page 19: Board Reset Elements

    FPGA, System MAX, HPS and FPGA respectively. Please refer to the following Table 3-4 for details.. Figure 3-11 Reset buttons on DE25-Standard Description of three Reset Buttons on DE25-Standard Table 3-4 Board Reference Signal Name Description Cold reset to the HPS, Ethernet PHY and USB host device. Active HPS_COLD_RESET_N low input which resets all HPS logics that can be reset.

  • Page 20: Clock Circuitry

    Figure 3-12 Reset buttons block diagram on DE25-Standard board Clock Circuitry Figure 3-13 shows the default frequency of all external clocks to the Agilex 5 SoC FPGA. A clock generator is used to distribute clock signals with low jitter. The three 50MHz clock signals connected to the FPGA are used as clock sources for user logic.

  • Page 21: Usb Type-C Connector

    150 MHz clock input DIFFERENTIAL SIGNALING USB Type-C Connector The USB Type-C connector on the DE25-Standard board is connected to three functions: USB blaster Figure 3-14, II interface, USB to UART for HPS and USB to UART for system MAX10. As shown in the USB type C connector is connected to a 3-port USB HUB.
  • Page 22 Another UART interface will be connected to the System MAX10. This bus allows users to monitor the status of the board from the host through the UART interface. Figure 3-14 Block diagram of the USB type-c functions on DE25-Standard USB to UART for System MAX10 The USB to UART interface is connected with the System MAX10.

  • Page 23: I2C Bus

    Please refer to section 3.9.3 for detailed. I2C Bus There are many devices controlled by the i2c interface on the DE25-Standard board, such as Audio codec, ADC sensor and accelerometer. Most of the devices on the board are connected to the i2c bus named FPGA_I2C_SCL/SDA, and this bus is also connected to the HPS I2C bus (HPS_I2C_SCL /SDA), so users can use FPGA or HPS Fabric to access these devices.

  • Page 24: Peripherals Connected To The Fpga

    Figure 3-17 Connections between the push-buttons and the Agilex 5 SoC FPGA. Schmitt trigger circuit is implemented and act as switch debounce in Figure 3-18 for the push-buttons connected. The four push-buttons named DE25-Standard www.terasic.com User Manual June 7, 2024...
  • Page 25 FPGA. When the switch is set to the DOWN position (towards the edge of the board), it generates a low logic level to the FPGA. When the switch is set to the UP position, a high logic level is generated to the FPGA DE25-Standard www.terasic.com User Manual...
  • Page 26 LEDs and Agilex 5 SoC FPGA. Table 3-7, Table 3-8 Table 3-9 list the pin assignment of user push-buttons, switches, and LEDs. Figure 3-20 Connections between the LEDs and the Agilex 5 SoC FPGA DE25-Standard www.terasic.com User Manual June 7, 2024...

  • Page 27: 7-Segment Displays

    PIN_AC22 LED [9] 1.2V 3.8.2 7-segment Displays The DE25-Standard board has six 7-segment displays. These displays are paired to display numbers Figure 3-21 in various sizes. shows the connection of seven segments (common anode) to pins on Agilex 5 SoC FPGA. The segment can be turned on or off by applying a low logic level or high logic level from the FPGA, respectively.
  • Page 28 Seven Segment Digit 3[4] 1.2V HEX3[5] PIN_CH89 Seven Segment Digit 3[5] 1.2V HEX3[6] PIN_CH92 Seven Segment Digit 3[6] 1.2V HEX4[0] PIN_CF92 Seven Segment Digit 4[0] 1.2V HEX4[1] PIN_CA92 Seven Segment Digit 4[1] 1.2V DE25-Standard www.terasic.com User Manual June 7, 2024...

  • Page 29: 2X20 Gpio Expansion Header

    Figure 3-22 shows the protection circuitry applied to all 36 data pins. Table 3-12 shows the pin assignment of the GPIO header. Figure 3-22 Connections between the GPIO header and Agilex 5 SoC FPGA DE25-Standard www.terasic.com User Manual June 7, 2024...

  • Page 30: Hsmc Connector

    FPGA host board by means of add-on daughter cards, which can address today’s high speed signaling requirements as well as low-speed device interface support. The HSMC interface support JTAG, clock outputs and inputs, high-speed serial I/O (transceivers), and DE25-Standard www.terasic.com User Manual...
  • Page 31 VCCIO6E~VCCIO6H to 3.3V, 2.5V and 1.8V to control the voltage level of the I/O pins. Table 3-14 lists the jumper settings of the JP5. Table 3-16 shows all the pin assignments of the HSMC connector. DE25-Standard www.terasic.com User Manual June 7, 2024...
  • Page 32 (SW10.3 ) on the board (see ). In the board's default setting, the JTAG interface of the HSMC connector is bypassed to keep the board JTAG chain DE25-Standard www.terasic.com User Manual June 7, 2024...
  • Page 33 Figure 3-25 HSMC JTAG Bypass Setting Switch Single-emded I/O One big difference between DE25-Standard and other previous DE series is that most FPGA I/O connected with HSMC connector can only use single-ended I/O standard because they are connected to the HVIO bank of Agilex 5 SoC. Other differential signal formats will not supported on this board.
  • Page 34 HSMC_RX_D_P[8] HSMC_D[39] PIN_AL25 CMOS I/O Depend on JP5 HSMC_RX_D_N[8] HSMC_D[40] PIN_AB8 CMOS I/O Depend on JP5 HSMC_TX_D_P[9] HSMC_D[41] PIN_AK25 CMOS I/O Depend on JP5 HSMC_TX_D_N[9] HSMC_D[42] PIN_Y8 CMOS I/O Depend on JP5 HSMC_RX_D_P[9] DE25-Standard www.terasic.com User Manual June 7, 2024...
  • Page 35 GTS Transceiver TX bit 0 HIGH SPEED HSMC_XCVR_TX_P[ DIFFERENTIAL I/O HSMC_GTS_TX_P[1] PIN_AR129 GTS Transceiver TX bit 1 HIGH SPEED HSMC_XCVR_TX_P[ DIFFERENTIAL I/O HSMC_GTS_TX_P[2] PIN_AN129 GTS Transceiver TX bit 1 HIGH SPEED HSMC_XCVR_TX_P[ DIFFERENTIAL I/O DE25-Standard www.terasic.com User Manual June 7, 2024...

  • Page 36: 24-Bit Audio Codec

    HSMC_XCVR_RX_P[ 3.8.5 24-bit Audio CODEC The DE25-Standard board offers high-quality 24-bit audio via the Analog Devices SSM2603 (same function as Wolfson WM8731) audio CODEC (Encoder/Decoder). This chip supports microphone- in, line-in, and line-out ports, with adjustable sample rate from 8 kHz to 96 kHz. The WM8731 is controlled via serial I2C bus, which is connected to HPS or Agilex 5 SoC FPGA through an I2C multiplexer.

  • Page 37: Hdmi Output

    Figure 3-27 Connections between the FPGA and HDMI Transmitter Chip Pin Assignment of HMDI Table 3-18 Signal Name FPGA Pin No. Description I/O Standard HDMI_TX_D0 PIN_CD134 Video Data bus 3.3V HDMI_TX_D1 PIN_CD135 Video Data bus 3.3V HDMI_TX_D2 PIN_CG134 Video Data bus 3.3V DE25-Standard www.terasic.com User Manual June 7, 2024...

  • Page 38: Tv Decoder

    3.3V 3.8.7 TV Decoder The DE25-Standard board is equipped with an Analog Device ADV7180 TV decoder chip. The ADV7180 is an integrated video decoder which automatically detects and converts a standard analog baseband television signals (NTSC, PAL, and SECAM) into 4:2:2 component video data, which is compatible with the 8-bit ITU-R BT.656 interface standard.

  • Page 39: Ir Receiver

    PIN_BM109 I2C Data 3.3V 3.8.8 IR Receiver The board comes with an infrared remote-control receiver module (model: IRM-V538/TR1), whose datasheet is provided in the directory \Datasheets\ IR Receiver and Emitter of DE25-Standard system DE25-Standard www.terasic.com User Manual June 7, 2024...

  • Page 40: Ir Emitter Led

    IR emitter LED with another IR receiver on the other side. Figure 3-30 Table 3-21 shows the connection of IR emitter LED to the FPGA. shows the pin assignment of IR emitter LED to the FPGA. DE25-Standard www.terasic.com User Manual June 7, 2024...

  • Page 41: Ddr4 Memory

    DDR4 Address[0] SSTL-12 DDR4_A[1] PIN_P114 DDR4 Address[1] SSTL-12 DDR4_A[2] PIN_V117 DDR4 Address[2] SSTL-12 DDR4_A[3] PIN_T117 DDR4 Address[3] SSTL-12 DDR4_A[4] PIN_M114 DDR4 Address[4] SSTL-12 DDR4_A[5] PIN_K114 DDR4 Address[5] SSTL-12 DDR4_A[6] PIN_V108 DDR4 Address[6] SSTL-12 DE25-Standard www.terasic.com User Manual June 7, 2024...
  • Page 42 DDR4 Data[17] 1.2-V POD DDR4_DQ[18] PIN_P95 DDR4 Data[18] 1.2-V POD DDR4_DQ[19] PIN_M84 DDR4 Data[19] 1.2-V POD DDR4_DQ[20] PIN_T98 DDR4 Data[20] 1.2-V POD DDR4_DQ[21] PIN_V98 DDR4 Data[21] 1.2-V POD DDR4_DQ[22] PIN_T84 DDR4 Data[22] 1.2-V POD DE25-Standard www.terasic.com User Manual June 7, 2024...

  • Page 43: Sdram Memory

    16-bit data line, control line, and address line connected to the FPGA. This chip uses the 1.8V LVCMOS signaling standard. Connections between the FPGA and SDRAM are shown in Figure 3-32, and the pin assignment is listed in Table 3-23. DE25-Standard www.terasic.com User Manual June 7, 2024...
  • Page 44 SDRAM Data[5] 1.8V DRAM_DQ[6] PIN_A23 SDRAM Data[6] 1.8V DRAM_DQ[7] PIN_B4 SDRAM Data[7] 1.8V DRAM_DQ[8] PIN_B20 SDRAM Data[8] 1.8V DRAM_DQ[9] PIN_B23 SDRAM Data[9] 1.8V DRAM_DQ[10] PIN_B26 SDRAM Data[10] 1.8V DRAM_DQ[11] PIN_B30 SDRAM Data[11] 1.8V DE25-Standard www.terasic.com User Manual June 7, 2024...

  • Page 45: A/D Converter And 2X5 Header

    3.8.12 A/D Converter and 2x5 Header The DE25-Standard has an analog-to-digital converter (LTC2308), which features low noise, eight- channel CMOS 12-bit. This ADC offers conversion throughput rate up to 500KSPS. The analog input range for all input channels can be 0 V to 4.096V. The internal conversion clock allows the external serial output data clock (SCLK) to operate at any frequency up to 40MHz.

  • Page 46: Mipi Connector

    Raspberry Pi MIPI Displayer module to implement a display application. Figure 3-36 shows the connections between the FPGA and 22-pin MIPI connector. Table 3-25 shows the pin assignment of 22-pin MIPI connector. DE25-Standard www.terasic.com User Manual June 7, 2024...
  • Page 47 MIPI Data 0 positive DPHY CAM_D_P[1] PIN_CH4 MIPI Data 1 positive DPHY CAM_D_N[0] MIPI Data 0 negative DPHY CAM_D_N[1] MIPI Data 1 negative DPHY CAM_I2C_SCL I2C clock 3.3V CAM_I2C_SDA I2C data 3.3V CAM_GPIO GPIO signal 3.3V DE25-Standard www.terasic.com User Manual June 7, 2024...

  • Page 48: Peripherals Connected To Hard Processor System (Hps)

    The pin assignment associated with Gigabit Ethernet interface is listed in Table 3-27. More information about the KSZ9031RN PHY chip and its datasheet, as well as the application notes, is available on the manufacturer’s website. DE25-Standard www.terasic.com User Manual June 7, 2024...
  • Page 49 Gigabit Ethernet is established once the LEDG lights on. State and Definition of LED Mode Pins Table 3-28 LED (State) LED (Definition) Link /Activity LEDG LEDY LEDG LEDY Link off 1000 Link / No Activity DE25-Standard www.terasic.com User Manual June 7, 2024...

  • Page 50: Uart To Usb

    1.8V 3.9.4 Micro SD Card Socket The board supports Micro SD card interface with x4 data lines. It serves not only an external storage for the HPS, but also an alternative boot option for DE25-Standard board. Figure 3-39 shows signals connected between the HPS and Micro SD card socket.

  • Page 51: 2-Port Usb Host

    When operating in Host mode, the device is powered by the two USB type-A ports. Figure 3-40 Table 3-31 shows the connections of USB PTG PHY to the HPS. lists the pin assignment of USBOTG PHY to the HPS. DE25-Standard www.terasic.com User Manual June 7, 2024...

  • Page 52: Accelerometer (G-Sensor)

    I2C interface. The I2C address of G-sensor is 0xA6/0xA7. More information about this chip can be found in its datasheet, which is available on manufacturer’s website or in the directory \Datasheet folder of DE25-Standard system CD. Figure 3-41 shows the connections between the HPS and G-sensor.

  • Page 53: 1X6 Header

    HPS and 1x6 pin header are shown in Figure 3-42, and the pin assignment of 1x6 pin header is listed in Table 3-33. Figure 3-42 Connections between the HPS and 1x6 Header DE25-Standard www.terasic.com User Manual June 7, 2024...

  • Page 54: 128X64 Dots Lcd

    FPGA Pin No. Description I/O Standard HPS_LCM_D_C PIN_P124 HPS LCM Data bit is Data/Command 3.3V HPS_LCM_RST_N PIN_T124 HPS LCM Reset 3.3V HPS_LCM_SPIM_CLK PIN_F12 SPI Clock 3.3V HPS_LCM_SPIM_MOSI PIN_Y124 SPI Master Output /Slave Input 3.3V DE25-Standard www.terasic.com User Manual June 7, 2024...

  • Page 55: Chapter 4 Dashboard Gui

    To use the dashboard system, users need to install the USB to UART driver on the host first, so that user can establish a connection with the DE25-Standard board. This section will describe how to install USB to UART driver on the windows OS host.
  • Page 56 Figure 4-2 Connect USB type-c cable to the board 2. Connect power to the DE25-Standard. Figure 4-3 Connect power to the board 3. Power on the DE25-Standard . Figure 4-4 Power on switch DE25-Standard www.terasic.com User Manual June 7, 2024...

  • Page 57: Run Dashboard Gui

    Figure 4-5 The CP2105 in the Device Manager Run Dashboard GUI Dashboard GUI software location Users can find it from the path: Tool\dashboard_gui\Dashboard.exe in the DE25-Standard system CD and copy it to the host PC. DE25-Standard www.terasic.com...
  • Page 58 4-7, there is a Start button at the bottom-left of the GUI window. Click it to run the program (Start will change to Stop), it will show the DE25-Standard status. Users can press Stop button to stop the status data transmission and display.
  • Page 59 Figure 4-8, once you press the “Start” button, it will show the status LED number on the DE25-Standard. For these LEDs function, please refer to section 2.2. Note that “CONF_DONE” stands for FPGA configure done status. There is no LED on DE25-Standard to display FPGA configure status.
  • Page 60 FPGA/Board/ Board2 Temperature: The Dashboard GUI will real-time show the fan speed, DE25-Standard ambient and FPGA temperature. Users can know the board temperature in time. The information will be refreshed per 1 second, and displays through diagram and number, as...
  • Page 61 Figure 4-10 Location of the board’s ambient temperature Fan RPM: It displays the real-time speed of the fan on the DE25-Standard, as shown in Figure 4-11. Figure 4-11 FAN RPM section 12V Power monitor: It displays the real-time 12V Power voltage and consumption current on Figure 4-12.
  • Page 62 Sampling Speed: It can change interval time that the Dashboard GUI sample the board status. Users can adjust it to 1s/10s/1min/Full Speed (0.1s) to sample the board status, as shown in Figure 4-13 Figure 4-14. Figure 4-13 Sampling speed section DE25-Standard www.terasic.com User Manual June 7, 2024...
  • Page 63 Figure 4-14 Options of sampling speed Board Information: There is a File page on the upper left of the Dashboard GUI program window, click the Board Information to get the current software version and the DE25-Standard version, as shown in Figure 4-15.
  • Page 64 Figure 4-16 Export the log file Figure 4-17 Export the log file in .csv format DE25-Standard www.terasic.com User Manual June 7, 2024...

  • Page 65: Chapter 5 Appendix

    Chapter 5 Appendix Revision History Version Change Log V0.9 Draft Version Copyright Statement Copyright © 2024 Terasic Inc. All Rights Reserved. DE25-Standard www.terasic.com User Manual June 7, 2024...

Table of Contents