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Terasic DE25-Standard User Manual

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DE25-Standard
User Manual
www.terasic.com
October 28, 2024

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Summary of Contents for Terasic DE25-Standard

  • Page 1 DE25-Standard www.terasic.com User Manual October 28, 2024...

  • Page 2: Table Of Contents

    Chapter 3 Using the DE25-Standard Board ..........11 3.1 Settings of FPGA Configuration Mode ..................11 3.2 Configuration of Agilex 5 SoC FPGA on DE25-Standard ............12 3.3 Board Status Elements ......................17 3.4 Board Reset Elements ....................... 18 3.5 Clock Circuitry ......................... 19 3.6 USB Type-C Connector ......................
  • Page 3 Dashboard GUI ................55 4.1 Setup for the Dashboard GUI ....................55 4.2 Run Dashboard GUI ......................... 57 Chapter 5 Appendix ..................65 5.1 Revision History ........................65 5.2 Copyright Statement ......................... 65 DE25-Standard www.terasic.com User Manual October 28, 2024...

  • Page 4: De25-Standard Development Kit

    Ethernet networking, MIPI interface and much more that promise many exciting applications. The DE25-Standard Development Kit contains all the tools needed to use the board in conjunction with a computer that runs the Microsoft Windows 10.

  • Page 5: Package Contents

    Fan (Installed) DE25-Standard System CD The DE25-Standard System CD contains all the documents and supporting materials associated with DE25-Standard, including the user manual, system builder, reference designs, and device datasheets. Users can download this system CD from the link: http://DE25-standard.terasic.com/cd/.

  • Page 6: Getting Help

    Getting Help Here are the addresses where you can get help if you encounter any problems:  Terasic Technologies  No.80, Fenggong Rd., Hukou Township, Hsinchu County, 303035 Taiwan Email: support@terasic.com Tel.: +886-3-575-0880 Website: DE25-standard.terasic.com DE25-Standard www.terasic.com User Manual October 28, 2024...

  • Page 7: Introduction To The De25-Standard Board

    This chapter provides an introduction to the design and features of the board. Layout and Components Figure 2-1 shows a photograph of the board that illustrates its layout and the location of connectors and key components. Figure 2-1 DE25-Standard development board (top view) DE25-Standard www.terasic.com User Manual October 28, 2024...

  • Page 8: Block Diagram Of The De25-Standard Board

    The DE25-Standard board has many features that allow users to implement a wide range of designed circuits, from simple circuits to multimedia projects. The following hardware is provided on the board:  FPGA  Agilex 5 SoC FPGA : A5ED013BB32AE4S (130K LEs) ...

  • Page 9: Memory Device

    5 SoC FPGA device to provide maximum flexibility for users. Users can configure the FPGA to implement any system design. Figure 2-2 Block diagram of DE25-Standard Detailed information about Figure 2-2 are listed below. FPGA Device  Agilex™ 5 SoC FPGA : A5ED013BB32AE4S ...

  • Page 10: Video Input

     5 user buttons (FPGA ×4, HPS ×1)  10 user switches (FPGA ×10)  11 user LEDs (FPGA ×10, HPS × 1)  1 HPS reset buttons (HPS_Cold_RESET_n)  Six 7-segment displays Sensors  Accelerometer (G-Sensor) on HPS DE25-Standard www.terasic.com User Manual October 28, 2024...
  • Page 11 Power  12V DC input DE25-Standard www.terasic.com User Manual October 28, 2024...

  • Page 12: Using The De25-Standard Board

    This chapter provides instructions for using the board and describes its peripherals. Settings of FPGA Configuration Mode When the DE25-Standard board is powered on, the FPGA is configured from QSPI FLASH or the HPS. The MSEL[2:0] switches are used to select the configuration scheme, implemented as a 4-pin...

  • Page 13: Configuration Of Agilex 5 Soc Fpga On De25-Standard

    The information is retained within QSPI Flash even if the DE25-Standard board is turned off. When the board is powered on, the configuration data in the QSPI Flash device is automatically loaded into the Agilex 5 SoC FPGA.
  • Page 14 The following explains step-by-step how to program the FPGA in JTAG mode. 1. Make sure the Quartus Pro and the driver of USB Blaster II are installed on your Host. 2. Open the Quartus Programmer tool, make sure the USB blaster II (“DE25-Standard Development Kit[USB-x]”)is found in “Hardware Setup..” tab.
  • Page 15 Figure 3-4 USB blaster II is found in Programmer 3. Open the Programmer and click “Auto Detect”, as shown in Figure 3-5 Figure 3-5 Detect FPGA device in JTAG mode DE25-Standard www.terasic.com User Manual October 28, 2024...
  • Page 16 5. Right click on the FPGA device and open the .sof file to be programmed, as shown in Figure 3-7. Figure 3-7 Open the .sof file to be programmed into the FPGA device 6. Select the .sof file to be programmed, as shown in Figure 3-8. DE25-Standard www.terasic.com User Manual October 28, 2024...
  • Page 17 Figure 3-8 Select the .sof file to be programmed into the FPGA device 7. Click the “Program/Configure” checkbox and click “Start” button to download the .sof file into the FPGA device, as shown in Figure 3-9. Figure 3-9 Program .sof file into the FPGA device DE25-Standard www.terasic.com User Manual October 28, 2024...

  • Page 18: Board Status Elements

    In addition to the 10 LEDs that the FPGA can control, there are 5 indicators that indicate the board status (see Figure 3-10). Table 3-3 lists the details. Figure 3-10 LED Indicators on the DE25-Standard LED Indicators Table 3-3 Board Reference LED Name Description Illuminates when 12V power is active. 3.3V Illuminates when 3.3V power is active.

  • Page 19: Board Reset Elements

    System MAX, CPU and FPGA. Table 3-4 lists the details. Figure 3-11 Reset buttons on DE25-Standard Description of the three Reset Buttons on the DE25-Standard Table 3-4 Board Reference Signal Name Description Cold reset to the HPS, Ethernet PHY and USB host device. Active HPS_COLD_RESET_N low input which resets all HPS logics that can be reset.

  • Page 20: Clock Circuitry

    Figure 3-12 Block diagram of reset buttons the DE25-Standard Clock Circuitry Figure 3-13 shows the default frequency of all external clocks fed to the Agilex 5 SoC FPGA. A clock generator is used to distribute clock signals with low jitter. The three 50 MHz clock signals connected to the FPGA are used as clock sources for user logic.

  • Page 21: Usb Type-C Connector

    150 MHz clock input DIFFERENTIAL SIGNALING USB Type-C Connector The USB Type-C connector on the DE25-Standard is connected to three functions: USB Blaster II interface, USB to UART for HPS and USB to UART for system MAX10. As shown in Figure 3-14, the USB Type-C connector is connected to a 3-port USB hub.
  • Page 22 Another serial port is connected to the System MAX10 to allow users to monitor the status of the board from the host through the UART interface. Figure 3-14 Block diagram of the USB type-c functions on DE25-Standard  USB to UART for System MAX10 The USB-to-UART interface is connected to the System MAX10.

  • Page 23: I2C Bus

    I2C Bus There are many devices controlled by the I2C interface on the DE25-Standard board, such as the Audio codec, ADC sensor and accelerometer. Most of the devices on the board are connected to the I2C bus named FPGA_I2C_SCL/SDA, and this bus is also connected to the HPS I2C bus (HPS_I2C_SCL /SDA), so users can access these devices from either the FPGA or HPS.

  • Page 24: Peripherals Connected To The Fpga

    Figure 3-18 for the connected buttons. The four buttons named KEY0, KEY1, KEY2, and KEY3 coming out of the Schmitt trigger device are connected directly to DE25-Standard www.terasic.com User Manual October 28, 2024...
  • Page 25 FPGA. When the switch is set to the DOWN position (towards the edge of the board), it sends a low logic level to the FPGA. When the switch is set to the UP position, a high logic level is sent to the FPGA DE25-Standard www.terasic.com User Manual...
  • Page 26 Agilex 5 SoC FPGA; driving its associated pin to a “low” logic level turn the LED “on”. Figure 3-20 shows the connections between LEDs and Agilex 5 SoC FPGA. Table 3-7, Table Table 3-9 list the pin assignment of user push-buttons, switches, and LEDs. DE25-Standard www.terasic.com User Manual October 28, 2024...

  • Page 27: 7-Segment Displays

    LED [9] 1.2V 3.8.2 7-segment Displays The DE25-Standard board has six 7-segment displays ideal for displaying numbers. Figure 3-21 shows the connection of the seven segments (common anode) to pins on the Agilex 5 SoC FPGA. Each segment can be turned on by applying a low logic level from the FPGA.
  • Page 28 Seven Segment Digit 3[4] 1.2V HEX3[5] PIN_CH89 Seven Segment Digit 3[5] 1.2V HEX3[6] PIN_CH92 Seven Segment Digit 3[6] 1.2V HEX4[0] PIN_CF92 Seven Segment Digit 4[0] 1.2V HEX4[1] PIN_CA92 Seven Segment Digit 4[1] 1.2V DE25-Standard www.terasic.com User Manual October 28, 2024...

  • Page 29: 2X20 Gpio Expansion Header

    36 data pins. Table 3-12 shows the pin assignment of the GPIO header. Figure 3-22 Connections between the GPIO header and Agilex 5 SoC FPGA DE25-Standard www.terasic.com User Manual October 28, 2024...

  • Page 30: Hsmc Connector

    FPGA peripherals on daughter cards, which can address today’s high speed signaling requirements as well as low-speed device interface support. The HSMC interface supports JTAG, clock outputs and inputs, high-speed serial I/O (transceivers), and single-ended signals. Signals on DE25-Standard www.terasic.com User Manual...
  • Page 31 VCCIO6E~VCCIO6H to 3.3V, 2.5V and 1.8V to control the voltage level of the I/O pins. Table 3-14 lists the settings for JP5. Table 3-16 shows the pin assignments of the HSMC connector. DE25-Standard www.terasic.com User Manual October 28, 2024...
  • Page 32 Users can enable this feature through a switch (SW10.3) on the board (see Figure 3-25). In the board's default setting, the JTAG interface of the HSMC connector is bypassed to keep the board JTAG chain DE25-Standard www.terasic.com User Manual October 28, 2024...
  • Page 33  Single-emded I/O One big difference between the DE25-Standard and other previous DE series boards is that most FPGA I/O connected to the HSMC connector can only use single-ended I/O standards because they are connected to the HVIO bank of the Agilex 5 SoC. Other differential signal formats are not supported on the DE25-Standard.
  • Page 34 HSMC_RX_D_P[8] HSMC_D[39] PIN_Y24 CMOS I/O Depend on JP5 HSMC_RX_D_N[8] HSMC_D[40] PIN_AB27 CMOS I/O Depend on JP5 HSMC_TX_D_P[9] HSMC_D[41] PIN_AB18 CMOS I/O Depend on JP5 HSMC_TX_D_N[9] HSMC_D[42] PIN_AB24 CMOS I/O Depend on JP5 HSMC_RX_D_P[9] DE25-Standard www.terasic.com User Manual October 28, 2024...
  • Page 35 GTS Transceiver TX bit 0 HIGH SPEED HSMC_XCVR_TX_P[ DIFFERENTIAL I/O HSMC_GTS_TX_P[1] PIN_AR129 GTS Transceiver TX bit 1 HIGH SPEED HSMC_XCVR_TX_P[ DIFFERENTIAL I/O HSMC_GTS_TX_P[2] PIN_AN129 GTS Transceiver TX bit 1 HIGH SPEED HSMC_XCVR_TX_P[ DIFFERENTIAL I/O DE25-Standard www.terasic.com User Manual October 28, 2024...

  • Page 36: 24-Bit Audio Codec

    HSMC_XCVR_RX_P[ 3.8.5 24-bit Audio CODEC The DE25-Standard board offers high-quality 24-bit audio via the Analog Devices SSM2603 (compatible with the Wolfson WM8731) audio CODEC (Encoder/Decoder). This chip supports microphone-in, line-in, and line-out ports, with adjustable sample rates from 8 kHz to 96 kHz. The WM8731 is controlled via the serial I2C bus, which is connected to the HPS or Agilex 5 SoC FPGA through an I2C multiplexer.

  • Page 37: Hdmi Output

    Figure 3-27. Detailed information on using the ADV7513 HDMI TX is available on the manufacturer’s website, or under the Datasheets\HDMI folder on the DE25-Standard System CD. Table 3-18 lists the HDMI Interface pin assignments and signal names relative to the FPGA.

  • Page 38: Tv Decoder

    3.3V 3.8.7 TV Decoder The DE25-Standard board is equipped with an Analog Device ADV7180 TV decoder chip. The ADV7180 is an integrated video decoder which automatically detects and converts a standard analog color composite baseband television signal (NTSC, PAL, and SECAM) into 4:2:2 component video data, which is compatible with the 8-bit ITU-R BT.656 interface standard.

  • Page 39: Ir Receiver

    PIN_BM109 I2C Data 3.3V 3.8.8 IR Receiver The board comes with an infrared remote-control receiver module (model: IRM-V538/TR1), whose datasheet is provided in the directory \Datasheets\ IR Receiver and Emitter of the DE25-Standard DE25-Standard www.terasic.com User Manual October 28, 2024...

  • Page 40: Ir Emitter Led

    IR emitter LED with another IR receiver on the other side. Figure 3-30 shows the connection of IR emitter LED to the FPGA. Table 3-21 shows the pin assignment of IR emitter LED to the FPGA. DE25-Standard www.terasic.com User Manual October 28, 2024...

  • Page 41: Ddr4 Memory

    EMIF IP of the FPGA. The DDR4 SDRAM on the board can run at a clock frequency of 1200 MHz. Figure 3-31 shows the connections between the DDR4 and the Agilex 5 SoC FPGA. Table 3-22 lists the pin assignments of the DDR4 and their I/O standards. DE25-Standard www.terasic.com User Manual October 28, 2024...
  • Page 42 DDR4_BG[0] PIN_AB105 Bank Group Select[0] SSTL-12 DDR4_CKE PIN_F105 DDR4 Clock Enable SSTL-12 DDR4_CK PIN_H108 DIFFERENTIAL 1.2-V DDR4 Clock p SSTL DDR4_CK_N PIN_F108 DIFFERENTIAL 1.2-V DDR4 Clock SSTL DDR4_CS_N PIN_K117 DDR4 Chip Select SSTL-12 DE25-Standard www.terasic.com User Manual October 28, 2024...
  • Page 43 DDR4 Data Strobe n[1] DDR4_DQS_N[2] PIN_M95 DIFFERENTIAL 1.2-V DDR4 Data Strobe n[2] DDR4_DQS_N[3] PIN_D95 DIFFERENTIAL 1.2-V DDR4 Data Strobe n[3] DDR4_DQS[0] PIN_B122 DIFFERENTIAL 1.2-V DDR4 Data Strobe p[0] DDR4_DQS[1] PIN_AG90 DDR4 Data Strobe p[1] DIFFERENTIAL 1.2-V DE25-Standard www.terasic.com User Manual October 28, 2024...

  • Page 44: Sdram Memory

    LVCMOS signaling standard. Connections between the FPGA and SDRAM are shown in Figure 3-32, and the pin assignment is listed in Table 3-23. Figure 3-32 Connections between the FPGA and SDRAM Pin Assignment of SDRAM Table 3-23 DE25-Standard www.terasic.com User Manual October 28, 2024...

  • Page 45: A/D Converter And 2X5 Header

    3.8.12 A/D Converter and 2x5 Header The DE25-Standard has a low noise, eight-channel CMOS 12-bit analog-to-digital converter (LTC2308). This ADC offers conversion throughput rate up to 500 KSPS. The analog input range for all input channels is 0 V to 4.096 V. The internal conversion clock allows the external serial output DE25-Standard www.terasic.com...
  • Page 46 3-33. More information about the A/D converter chip is available in its datasheet, which can be found on the manufacturer’s website or in the directory \datasheet of the DE25-Standard system CD. Figure 3-33 Signals of the 2x5 Header Figure 3-34 shows the connections between the FPGA, 2×5 header, and the A/D converter.

  • Page 47: Mipi Connector

    FPGA and the 22-pin MIPI connector. Table 3-25 shows the pin assignments of the 22-pin MIPI connector. Figure 3-35 MIPI camera module connects to the board via cable DE25-Standard www.terasic.com User Manual October 28, 2024...

  • Page 48: Peripherals Connected To The Hard Processor System (Hps)

    This section introduces the interfaces connected to the HPS section of the Agilex 5 SoC FPGA. Users can access these interfaces via the HPS processors. 3.9.1 User Push-buttons and LEDs Similar to the FPGA, the HPS is directly connected to its own pushbutton and LED through its GPIO DE25-Standard www.terasic.com User Manual October 28, 2024...

  • Page 49: Gigabit Ethernet

    1.8V HPS_ENET_TX_DATA[1] PIN_AD134 GMII and MII transmit data[1] 1.8V HPS_ENET_TX_DATA[2] PIN_J134 GMII and MII transmit data[2] 1.8V HPS_ENET_TX_DATA[3] PIN_AG120 GMII and MII transmit data[3] 1.8V HPS_ENET_TX_CLK PIN_P132 GMII and MII transmit clock 1.8V DE25-Standard www.terasic.com User Manual October 28, 2024...

  • Page 50: Uart To Usb

    HPS. Figure 3-38 shows the connections between the FPGA (HPS), system MAX10, CP2105 chip, and the USB Type-C connector. Table 3-29 lists the pin assignments of the UART interface connected to the HPS. DE25-Standard www.terasic.com User Manual October 28, 2024...

  • Page 51: Micro Sd Card Socket

    3.9.4 Micro SD Card Socket The board supports a Micro SD card interface with 4 data lines. It serves not only as an external storage for the HPS but also as an alternative boot option for the DE25-Standard board. Figure 3-39 shows the signals connected between the HPS and the Micro SD card socket.

  • Page 52: 2-Port Usb Host

    HPS_USB_DATA[6] PIN_N134 HPS USB_DATA[6] 1.8V HPS_USB_DATA[7] PIN_T132 HPS USB_DATA[7] 1.8V HPS_USB_DIR PIN_W134 Direction of the Data Bus 1.8V HPS_USB_NXT PIN_AL120 Throttle the Data 1.8V HPS_USB_STP PIN_U135 Stop Data Stream on the Bus 1.8V DE25-Standard www.terasic.com User Manual October 28, 2024...

  • Page 53: Accelerometer (G-Sensor)

    I2C interface. The I2C address of the G-sensor is 0xA6/0xA7. More information about this chip can be found in its datasheet, which is available on the manufacturer’s website or in the \Datasheet folder of the DE25-Standard system CD. Figure 3-41 shows the connections between the HPS and the G-sensor.

  • Page 54: 128×64 Pixel Lcd

    The default setting for the LCD backlight power is OFF (the pins of header JP4 are open). Table 3-34 lists the pin assignments between the LCD module and the Agilex 5 SoC FPGA. DE25-Standard www.terasic.com User Manual October 28, 2024...
  • Page 55 PIN_P124 HPS LCM Data bit is Data/Command 1.8V HPS_LCM_RST_N PIN_T124 HPS LCM Reset 1.8V HPS_LCM_SPIM_CLK PIN_F127 SPI Clock 1.8V HPS_LCM_SPIM_MOSI PIN_Y124 SPI Master Output /Slave Input 1.8V HPS_LCM_SPIM_SS PIN_AB124 SPI Slave Select 1.8V DE25-Standard www.terasic.com User Manual October 28, 2024...

  • Page 56: Chapter 4 Dashboard Gui

    Setup for the Dashboard GUI To use the dashboard system, users need to first install the USB-to-UART driver on the host to establish a connection with the DE25-Standard board. This section will describe how to install USB- to-UART drivers on the Windows OS host.
  • Page 57 1. Connect the board’s USB Type-C connector to the host PC USB port through a USB Type-C cable. Figure 4-2 Connect USB type-c cable to the board 2. Connect power to the DE25-Standard. Figure 4-3 Connect power to the board 3.

  • Page 58: Run Dashboard Gui

    Figure 4-5 The CP2105 in the Device Manager Run Dashboard GUI  Dashboard GUI software location Users can find it from the path: Tool\dashboard_gui\Dashboard.exe in the DE25-Standard system CD and copy it to the host PC. DE25-Standard www.terasic.com User Manual...
  • Page 59 4-7, there is a Start button at the bottom-left of the GUI window. Click it to run the program (Start will change to Stop). The DE25-Standard status will be displayed. Users can press Stop button to stop the status data transmission and display.
  • Page 60 4-8, once you press the “Start” button, it will show the  status LED number on the DE25-Standard. Please refer to section 2.2 for a description of these LEDs. Note that “CONF_DONE” indicates FPGA configuration is done. There is no LED on the DE25-Standard to display FPGA configuration status.
  • Page 61 Figure 4-8 FPGA Status section  FPGA/Board/ Board2 Temperature: The Dashboard GUI will show in real-time the fan speed, DE25-Standard ambient and FPGA temperature. This information will be refreshed once per second, and be displayed both numerically and graphically as shown in Figure 4-9.
  • Page 62 Figure 4-10 Location of the board’s ambient temperature  Fan RPM: This displays the real-time speed of the fan on the DE25-Standard, as shown in Figure 4-11. Figure 4-11 FAN RPM section DE25-Standard www.terasic.com User Manual October 28, 2024...
  • Page 63  12V Power monitor: This displays the real-time voltage on the 12V Power input and consumption current on the DE25-Standard, as shown in Figure 4-12. Figure 4-12 Power Monitor Section  Sampling Speed: This sets the sampling interval period used by the Dashboard GUI to 1s, 10s, 1min or Full Speed (0.1s), as shown in...
  • Page 64 Log File: On the upper left of the Dashboard GUI program window, click “Export...” in the File menu to save the board temperature, fan speed and voltage data in .csv format, as shown in Figure 4-16 Figure 4-17. DE25-Standard www.terasic.com User Manual October 28, 2024...
  • Page 65 Figure 4-16 Export the log file Figure 4-17 Export the log file in .csv format DE25-Standard www.terasic.com User Manual October 28, 2024...

  • Page 66: Chapter 5 Appendix

    Appendix Revision History Version Change Log V1.0 Initail version V1.1 Modify some error V1.2 Modify the content according to Prof. Stephen A. Edwards’s review Copyright Statement Copyright © Terasic Inc. All Rights Reserved. DE25-Standard www.terasic.com User Manual October 28, 2024...

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