Terasic DE5a-Net User Manual
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Terasic DE5a-Net User Manual

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DE5a-Net OpenCL
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www.terasic.com
March 23, 2018

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  • Page 1 DE5a-Net OpenCL www.terasic.com March 23, 2018...

  • Page 2: Table Of Contents

    CONTENTS DE5A-NET OPENCL CHAPTER 1 ..........................3 1.1 S ............................3 YSTEM EQUIREMENT 1.2 O CL A ............................4 RCHITECTURE OPENCL FOR WINDOWS CHAPTER 2 ........................5 2.1 S ............................5 OFTWARE NSTALLATION 2.2 E ............................8 NVIRONMENT ONFIGURE 2.3 O CL E ..........................

  • Page 3: De5A-Net Opencl

    OpenCL development environment for DE5a-Net board, and how to compile and execute the example projects for DE5a-Net. Note that OpenCL coding instruction is not introduced in this document, but the user can refer to Intel FPGA SDK for OpenCL Programming Guide for more details.

  • Page 4: Open Cl Architecture

    1-1. OpenCL kernel is compiled with Intel FPGA OpenCL compiler provided by the Altera OpenCL SDK. The Host Program is compiled by Visual Studio C/C++ in Windows or GCC on Linux. Figure 1-1 Intel FPGA OpenCL Architecture DE5a-Net OpenCL www.terasic.com March 23, 2018...

  • Page 5: Opencl For Windows

    OpenCL for Windows This chapter describes how to set up DE5a-Net OpenCL development environment on 64-bit Windows, and how to compile and test the OpenCL examples for DE5a-Net. For more details about Intel FPGA OpenCL started guide, please refer to: https://www.altera.com/en_US/pdfs/literature/hb/opencl-sdk/aocl_getting_started.pdf...
  • Page 6  DE5a-Net OpenCL BSP (Board Support Package) After Quartus II and OpenCL SDK are installed, download the DE5ANET_E1_OpenCL_BSP _17.1.zip DE5a-Net windows BSP from the web site: http://de5a-net.terasic.com/cd Then, decompress DE5ANET_E1_OpenCL_BSP_17.1.zip to the “de5a_net_e1” folder under the folder “C:\intelFPGA_pro\17.1\hld\board”, as shown in...
  • Page 7 Figure 2-2 DE5a-Net OpenCL BSP Content For more details about DE5a-Net OpenCL BSP, please refer to the Table Table 1 Windows BSP File File or Folder Description board_env.xml eXtensible Markup Language (XML) file that describes the Reference Platform to the Intel FPGA SDK for OpenCL.

  • Page 8: Environment Configure

    Developers need to create and edit some environment variable that Intel FPGA OpenCL SDK can find the kit location of DE5a-Net correctly Now, here are the procedures to create the required environment variable on Windows 7: Open the Start menu and right click on Computer. Select Properties.
  • Page 9 Figure 2-5 Figure 2-6, so the OpenCL SDK can find the binary file provided by OpenCL BSP. Figure 2-5 Select “Path” and click “Edit” bottom Figure 2-6 Edit PATH environment variable DE5a-Net OpenCL www.terasic.com March 23, 2018...
  • Page 10 In Command Prompt window, type “aocl version” command, and make sure the version of the OpenCL SDK is listed as shown in Figure 2-8. Figure 2-8 Version of OpenCL SDK  Target Board In Command Prompt window, type “aoc -list-boards” command, and make sure “de5a_net_e1” DE5a-Net OpenCL www.terasic.com March 23, 2018...
  • Page 11 Board list as shown in Figure 2-9. Figure 2-9 ‘de5a_net_e1’ is listed in Board list For more information about the aoc and aocl, refer to the ‘aoc -h’ and ‘aocl help’ command. DE5a-Net OpenCL www.terasic.com March 23, 2018...

  • Page 12: Initializing The Fpga For Using With Open Cl

     Board Setup To use the DE5a-Net Arria 10 FPGA Development Kit with the Intel FPGA SDK for OpenCL, you must follow the below procedures to set up DE5a-Net board on your PC as shown in Figure 2-10. Make sure your PC is powered off.
  • Page 13 Figure 2-11 Bring up the FPGA board Perform a soft reboot (sometimes called a warm reboot) of your host system causes your host system to recognize the DE5a-Net Arria 10 FPGA Development Kit PCIe card.  Driver Installation Your system must recognize the card so that the Intel FPGA SDK for OpenCL driver can be loaded.
  • Page 14 “Install this driver software anyway” as shown in Figure 2-13 and go on. Figure 2-13 windows security When the installation is successful, Jungo WinDriver and FPGA Accelerator board can be found in the PC Device Manage as shown in Figure 2-14. DE5a-Net OpenCL www.terasic.com March 23, 2018...
  • Page 15 Before flash programming, the programmer will ask users which startup configuration image area will be used as shown in Figure 2-15. This is because DE5a-Net provides two startup configuration image areas, called as Factory Image and User Image. We recommend users to key in ‘1’ to select User Image area.
  • Page 16 Figure 2-16 Aocl Flash Successfully To make sure a correct image is used when FPGA boots up, please make sure the dip switch SW3.4 DE5a-Net OpenCL www.terasic.com March 23, 2018...
  • Page 17 DE5a-Net is changed to the correct location. If a User Image area is selected, the dip switch SW3.4 on the DE5a-Net should be moved to Up position as shown in Figure 2-17. Figure 2-17 Set SW3.4 to Up Position (User Image Page) After flash programming is done successfully and SW3.4 is set to correct position, developers...

  • Page 18: Open Cl Runtime Verify

    Note: It is strongly recommended that users set the PCIe speed at Gen 3 in the BIOS on the host PC, so that the DE5a-Net negotiates with the host PC at Gen3 as the link speed. If your PC supports PCIe Gen3x8, but it gets incorrect detected information, you can modify the PCIe settings in the BIOS, and reboot.
  • Page 19 OpenCL image. If the programming message displays “Program succeed” as shown in Figure 2-19, it means the hello_world OpenCL image is programmed into the FPGA successfully. Figure 2-19 Aocl Program Successfully DE5a-Net OpenCL www.terasic.com March 23, 2018...

  • Page 20: Compile And Test Open Cl Project

    This section will show how to compile and test OpenCL kernel and OpenCL Host Program for the vector_add project. Developers can use the same procedures to compile and test other OpenCL examples for DE5a-Net.  Compile OpenCL Kernel The utility aoc (Altera SDK for OpenCL Kernel Compiler) is used to compile the OpenCL kernel.
  • Page 21 “BUILDBuild Solution” to build host program. When build process is successful, you will see successful message as show in Figure 2-22. The execute file is generate in: “C:\intelFPGA_pro\17.1\hld\board\de5a_net_e1\tests\vector_add\bin\host.exe” Figure 2-22 Host Program Build Successfully DE5a-Net OpenCL www.terasic.com March 23, 2018...
  • Page 22 Firstly, In Command Prompt window, type “cd C:\intelFPGA_pro\17.1\hld\board\de5a_net_e 1\tests\vector_add\bin” to go to vector_add\bin project folder. Then, execute “host.exe”. Figure 2-23 is the screen shot when the test is successful. Figure 2-23 Host App Running successfully DE5a-Net OpenCL www.terasic.com March 23, 2018...

  • Page 23: Opencl For Linux

    This chapter describe how to setup DE5a-Net OpenCL development environment on 64-bit Linux (Red Hat Enterprise Linux 6.5/CentOS 7.0 are recommended), and how to compile and test the OpenCL examples for DE5a-Net. For more details about Altera OpenCL, please refer to Intel FPGA SDK for OpenCL Getting Started document: https://www.altera.com/en_US/pdfs/literature/hb/opencl-sdk/aocl_getting_started.pdf...
  • Page 24 Quartus II software uses the built-in USB-Blaster II drivers on Linux to access USB-Blaster II download cable on DE5a-Net. but after installing the Quartus II software with built-in drivers, user need to change the port permission for USB-Blaster II via issuing ‘gedit /etc/udev/rules.d/51-usbblaster.rules’...
  • Page 25 You must also have sudo or root privileges.  DE5a-Net OpenCL BSP (Board Support Package) After Quartus II and OpenCL SDK are installed, please download the DE5ANET_E1_Open CL_BSP_17.1.tar.gz DE5a-Net linux BSP from the web site: http://de5a-net.terasic.com/cd Then, decompress DE5ANET_E1_OpenCL_BSP_17.1.tar.gz to the “de5a_net_e1” folder under the folder "/root/intelFPGA_pro/17.1/hld/board", where assumed Quartus II is installed on the folder...
  • Page 26 For more details about DE5a-Net OpenCL BSP, please refer to the Table Table 2 Linux BSP File File or Folder Description board_env.xml eXtensible Markup Language (XML) file that describes the Reference Platform to the Intel FPGA SDK for OpenCL. hardware Contains the Intel Quartus Prime project templates for the a10gx board variant.

  • Page 27: Environment Configure

    INTELFPGAOCLSDKROOT and PATH environment variables manually. And the developers need to create an environment variable for the DE5a-Net board AOCL_BOARD_PACKAGE_ROOT so that the Intel FPGA OpenCL SDK is able to find the kit location of DE5a-Net correctly, and set its value as: "$ INTELFPGAOCLSDKROOT "/board/de5a_net_e1”...
  • Page 28 In the Linux terminal, type “aoc -list-boards” command, and make sure “de5a_net_e1” is listed in Board list as shown in Figure 3-4. Figure 3-4 ‘de5a_net_e1’ is Listed in Board List For more information about the aoc and aocl, refer to the ‘aoc -h’ and ‘aocl help’ command. DE5a-Net OpenCL www.terasic.com March 23, 2018...

  • Page 29: Initializing The Fpga For Use With Open Cl

     Board Setup To use the DE5a-Net Arria 10 FPGA Development Kit with the Intel FPGA SDK for OpenCL, you must follow the below procedures to set up DE5a-Net board on your PC as shown in Figure 3-5. Make sure your PC is powered off.
  • Page 30 Figure 3-6 Bring up the FPGA Borad Use the /sbin/reboot command to perform a soft reboot of your host system causes your host system to recognize the DE5a-Net Arria 10 FPGA Development Kit PCIe card.  Driver Installation Your system must recognize the card so that the Intel FPGA SDK for OpenCL driver can be loaded.
  • Page 31 Before flash programming, the programmer will ask users which startup configuration image area will be used as shown in Figure 3-9. This is because DE5a-Net provides two startup configuration image areas, called as Factory Image and User Image. We recommend users to key in ‘1’ to select User Image area.
  • Page 32 To make sure a correct image is used when FPGA boots up, please make sure the dip switch SW3.4 on DE5a-Net is changed to the correct location. If a User Image area is selected, the dip switch SW3.4 on the DE5a-Net should be moved to Up position as shown in Figure 3-11.
  • Page 33 Figure 3-11 Set SW3.4 to Up Position (User Image Page) After flash programming is done successfully and SW3.4 is set to correct position, developers must power off DE5a-Net board, then turn it back on, and restart the PC. DE5a-Net OpenCL www.terasic.com...

  • Page 34: Open Cl Runtime Verify

    Note: It is strongly recommended that users set the PCIe speed at Gen 3 in the BIOS on the host PC, so that DE5a-Net negotiates with the host PC at Gen3 as the link speed. If your PC support PCIe Gen3x8, but it gets incorrect detected information, you can modify the PCIe settings in the BIOS, and reboot.
  • Page 35 “aocl program acl0 hello_world.aocx” to configure the FPGA with hello_world.aocx OpenCL image. If the programming message displays “Program succeed” as shown in Figure 3-13, it means the hello_world OpenCL image is programmed into the FPGA correctly. Figure 3-13 Aocl Program Successfully DE5a-Net OpenCL www.terasic.com March 23, 2018...

  • Page 36: Compile And Test Open Cl Project

    This section will show how to compile and run the OpenCL kernel and OpenCL Host Program for the vector_add example project. Developers can use the same procedures to compile and test other OpenCL examples (included in the kit) for DE5a-Net.  Compile OpenCL Kernel In the terminal, type “cd /root/intelFPGA_pro/17.1/hld/board/de5a_net_e1/tests/vector_add”...
  • Page 37 FPGA with the OpenCL Image vector_add.aocx. Then, launch the compiled Host Program to start vector_add execute file for test. In the terminal type “./host”. Figure 3-16 shows the execution is successful. Figure 3-16 Host App Running successfully DE5a-Net OpenCL www.terasic.com March 23, 2018...

  • Page 38: Chapter 4 Appendix

    Chapter 4 Appendix Windows10 x64 OpenCL Driver Install Because the win10 system requires the signature of the .inf file, sometimes, the driver of the PCIE (without signature) fails to be installed after running aocl install. DE5a-Net OpenCL www.terasic.com March 23, 2018...
  • Page 39 As a solution, it needs to disable the driver signature, and then manually install the PCIe driver. The steps are as following: A. Disable the driver signature in the Win10 system 1.Click Home，enter “All settings”. 2. Access “Update & Security”. DE5a-Net OpenCL www.terasic.com March 23, 2018...
  • Page 40 3.Find Recovery. Click “Restart now” below “Advanced start-up”,restart the PC. 4.After restarting, choose “Troubleshoot”. DE5a-Net OpenCL www.terasic.com March 23, 2018...
  • Page 41 5.Choose “Advanced options”. 6.Choose "Start-up Settings". DE5a-Net OpenCL www.terasic.com March 23, 2018...
  • Page 42 7.Click “Restart”. 8.Enter "F7" to disable driver signature. DE5a-Net OpenCL www.terasic.com March 23, 2018...
  • Page 43 PCI Device with a yellow exclamation mark. Right Click --> Update Drivers - PCI Device --> Browse my computer for driver software 2.Choose “Let me pick from a list of available drivers on my computer”，Click “Next”. DE5a-Net OpenCL www.terasic.com March 23, 2018...
  • Page 44 3.Continue choose “Next”. 4.Choose “Have Disk ...” DE5a-Net OpenCL www.terasic.com March 23, 2018...
  • Page 45 5.Click Browse，locate BSP to de5a_net_e1/windows64/driver/ acl_boards_de5a_net_e1.inf， Click “OK”. 6.Select “Terasic FPGA Accelerator-DE5a-NET 1150K E1”, Click "Next" to continue the installation. DE5a-Net OpenCL www.terasic.com March 23, 2018...
  • Page 46 7.Select “Install this driver software anyway” in the pop-up “Windows Security” window. 8.Installation complete. DE5a-Net OpenCL www.terasic.com March 23, 2018...
  • Page 47 9.In the device manager, the Jungo Windriver and the DE5a-Net PCIE driver are both installed successfully. DE5a-Net OpenCL www.terasic.com March 23, 2018...

  • Page 48: Revision History

    Revision History Version Change Log V1.0 Initial Version Copyright Statement Copyright © 2018 Terasic Inc. All Rights Reserved. DE5a-Net OpenCL www.terasic.com March 23, 2018...

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