Voltage Reference Circuit; Analog Front End (Afe) - Analog Devices EVAL-AD4050-ARDZ User Manual

User Guide
EVALUATION BOARD HARDWARE

VOLTAGE REFERENCE CIRCUIT

In the factory default configuration, the on board
provides a 2.5 V reference voltage (VREF) to the AD4050/AD4052
REF input. The VREF sets the input range of the AD4050/AD4052,
as described in the AD4050 and AD4052 data sheets. By default,
the MAX6070 is powered by the 3.3 V analog rail. A 2.2 μF VREF
decoupling capacitor (C34) is located next to the AD4050/AD4052
REF pin to ensure a stable 2.5 V VREF voltage during the conver-
sion time of the SAR ADC core.

ANALOG FRONT END (AFE)

The AFE components provide signal conditioning between the
signal generator outputs and the AD4050/AD4052 analog inputs
(IN+ and IN− pins). In the factory default configuration, the AFE
consists of the following components:
SMA connectors for the positive and negative inputs (J1 and J2,
►
respectively)
SMA connector for an optional common-mode voltage (VCM)
►
source (J3)
Passive filter network for signal generator noise and/or anti-alias-
►
ing filtering (see Figure 11)
MAX44260 op amps in 6-lead SC70 footprint configured as
►
unity-gain buffers by default (see
RC kickback filter at the AD4050/AD4052 inputs
►
The Analog Inputs section provides instructions for interfacing the
signal generator and the SMA inputs on the EVAL-AD4050-ARDZ/
EVAL-AD4052-ARDZ.
By default, the amplifiers are configured as unity-gain buffers, but
optional passive components are included in the design to support
noninverting with gain, single-pole active filter, and Sallen-Key filter
configurations.
By default, all amplifiers are powered with a single supply with VEE
connected to GND and VCC supplied by VSUPPLY = 3.3 V. See
the Power Supplies section for more details.
The shutdown pins on the AFE amplifiers can optionally be rout-
ed to the GP0 pin on the AD4050/AD4052 via JP3 and JP4
jumpers. This allows performance and power measurements using
the DEV_EN control signal from the AD4050/AD4052 to power-cy-
cle the amplifiers in between conversions. See the AD4050 and
AD4052 data sheets for more information on the DEV_EN control
signal for dynamic power cycling of the AFE.
analog.com
MAX6070 (U4)
Figure 12)
EVAL-AD4050/AD4052
Figure 11. Signal and Common-Mode Inputs and Input Filter
Figure 12. Default Amplifier Circuit Simplified Schematics
Analog Inputs
This section provides guidance for driving the EVAL-AD4050-
ARDZ/EVAL-AD4052-ARDZ with a precision signal generator for
ADC performance evaluation.
The AD4050/AD4052 input range is set by the VREF voltage. In the
factory default configuration, the on board
2.5 V VREF (see Voltage Reference Circuit
AD4050/AD4052 input is 0 V to 2.5 V on either input (IN+ and IN−)
for a resulting maximum differential input swing of 2.5 V peak and 5
V p-p.
Figure 13. AD4050/AD4052 Input Range
By default, the MAX44260 amplifiers driving the AD4050/AD4052
analog inputs are configured as unity-gain buffers, so the signal on
their noninverting inputs must also be limited to 0 V to 2.5 V. When
MAX6070 generates a
section). Therefore, the
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