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Cypress Semiconductor Z9973 Specification Sheet

3.3v, 125-mhz, multi-output zero delay buffer
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Features
• Output frequency up to 125 MHz
• 12 clock outputs: frequency configurable
• 350 ps max output-to-output skew
• Configurable output disable
• Two reference clock inputs for dynamic toggling
• Oscillator or PECL reference input
• Spread spectrum-compatible
• Glitch-free output clocks transitioning
• 3.3V power supply
• Pin-compatible with MPC973
• Industrial temperature range: –40°C to +85°C
• 52-pin TQFP package

Block Diagram

PECL_CLK
PECL_CLK#
VCO_SEL
PLL_EN
REF_SEL
Phase
TCLK0
0
Detector
1
TCLK1
LPF
TCLK_SEL
FB_IN
FB_SEL2
MR#/OE
Power-On
Reset
/4, /6, /8, /12
/4, /6, /8, /10
2
SELA(0,1)
/2, /4, /6, /8
2
SELB(0,1)
/4, /6, /8, /10
2
SELC(0,1)
Sync Pulse
2
FB_SEL(0,1)
Data Generator
SCLK
Output Disable
Circuitry
SDATA
INV_CLK
Cypress Semiconductor Corporation
Document #: 38-07089 Rev. *D
3.3V, 125-MHz, Multi-Output Zero Delay Buffer
Sync
D Q
Frz
0
VCO
1
Sync
D Q
Frz
Sync
D Q
Frz
Sync
D Q
Frz
0
Sync
D Q
/2
1
Frz
Sync
D Q
Frz
12
•
3901 North First Street
[1]
Table 1. Frequency Table
VC0_SEL
FB_SEL2
FB_SEL1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
Note:
1.
x = the reference input frequency, 200 MHz < F
.

Pin Configuration

QA0
QA1
QA2
QA3
52 51 50 49 48 47 46 45 44 43 42 41 40
VSS
QB0
1
MR#/OE
2
QB1
SCLK
3
QB2
SDATA
4
FB_SEL2
5
QB3
PLL_EN
6
Z9973
REF_SEL
7
TCLK_SEL
8
QC0
TCLK0
9
TCLK1
10
QC1
11
PECL_CLK
QC2
12
PECL_CLK#
13
VDD
QC3
14 15 16 17 18 19 20 21 22 23 24 25 26
FB_OUT
SYNC
•
San Jose
•
Z9973
FB_SEL0
F
VC0
0
0
8x
0
1
12x
1
0
16x
1
1
20x
0
0
16x
0
1
24x
1
0
32x
1
1
40x
0
0
4x
0
1
6x
1
0
8x
1
1
10x
0
0
8x
0
1
12x
1
0
16x
1
1
20x
< 480 MHz.
VCO
VSS
39
QB0
38
VDDC
37
QB1
36
VSS
35
QB2
34
VDDC
33
QB3
32
FB_IN
31
VSS
30
29
FB_OUT
28
VDDC
27
FB_SEL0
CA 95134
•
408-943-2600
Revised December 21, 2002
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Summary of Contents for Cypress Semiconductor Z9973

  • Page 1: Block Diagram

    PECL_CLK Sync PECL_CLK# Sync FB_OUT Sync SYNC • 3901 North First Street • San Jose Z9973 FB_SEL1 FB_SEL0 < 480 MHz. 52 51 50 49 48 47 46 45 44 43 42 41 40 VDDC Z9973 VDDC FB_IN FB_OUT VDDC...

  • Page 2: Pin Description

    Serial Data Input. Input data is clocked to the internal register to enable/disable individual outputs. This provides flexibility in power management. 3.3V Power Supply for Output Clock Buffers. 3.3V Supply for PLL. Common Ground. Z9973 Page 2 of 9 [+] Feedback...

  • Page 3: Functional Description

    SELA1 SELA0 Zero Delay Buffer When used as a zero delay buffer, the Z9973 will likely be in a nested clock tree application. For these applications the Z9973 offers a low-voltage PECL clock input as a PLL reference. This allows the user to use LVPECL as the primary clock distribution device to take advantage of its far superior skew performance.
  • Page 4 SYNC SYNC SYNC SYNC SYNC SYNC SYNC Document #: 38-07089 Rev. *D 1:1 Mode 2:1 Mode 3:1 Mode 3:2 Mode 4:1 Mode 4:3 Mode 6:1 Mode Figure 1. Sync Output Waveforms Z9973 Page 4 of 9 [+] Feedback...

  • Page 5: Power Management

    Power Management The individual output enable/freeze control of the Z9973 allows the user to implement unique power management schemes into the design. The outputs are stopped in the logic “0” state when the freeze control bits are activated. The serial input register contains one programmable freeze enable bit for 12 of the 14 output clocks.

  • Page 6: Maximum Ratings

    QA and QB @ 25 MHz, QC @ 50 MHz, C = 30 pF = 3.3V ±10%, T = –40 C to +85 C) Conditions 0.8V to 2.0V Z9973 and V should be constrained to ) < V or V Min. Typ.

  • Page 7: Ordering Information

    Q ( 2) Q ( 4) Q ( 6) Q ( 8) (all outputs) (all outputs) [6,7] [7,8] QFB = ( 8) Package Type Z9973 Min. Typ. Max. Units TCYCLE TCYCLE /2 – 750 /2 + 750 ± 100 –225 –25...
  • Page 8 The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Z9973 51-85131-**...
  • Page 9 Document Title: Z9973 3.3V, 125 MHz Multi-Output Zero Delay Buffer Document Number: 38-07089 Rev. ECN No. Issue Date 107125 06/06/01 108067 07/03/01 111799 02/06/02 116452 07/30/02 122774 12/21/02 Document #: 38-07089 Rev. *D Orig. of Change Description of Change Convert from IMI to Cypress...

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