1. Manuals
  2. Brands
  3. Cypress Semiconductor Manuals
  4. Computer Hardware
  5. CY25566
  6. Specification sheet

Cypress Semiconductor CY25566 Specification Sheet

Cypress spread spectrum clock generator specification sheet
Hide thumbs
1
2
3
4
5
6
7
8
9

Advertisement

Table of Contents

Features
• 25- to 200-MHz operating frequency range
• Wide range of spread selections (9)
• Accepts clock or crystal inputs
• Provides four clocks
— SSCLK1a
— SSCLK1b
— SSCLK2
— REFOUT
• Low-power dissipation
— 3.3V = 70 mW (typical @ 40 MHz, no load)

Block Diagram

300K
Xin/
1
CLK
Xout
16
VDD
4
VSS
5
11
VSS
14
VSS
10
SSCC
Cypress Semiconductor Corporation
Document #: 38-07429 Rev. *B
Spread Spectrum Clock Generator
REFERENCE
DIVIDER
PD
CP
MODULATION
FEEDBACK
CONTROL
DIVIDER
INPUT
DECODER
LOGIC
VDD
VDD
20 K
20 K
RANGE
CONTROL
20 K
20 K
VSS
VSS
6
12
13
7
S1
S0
S2
S3
•
3901 North First Street
• Center spread modulation
• Low cycle-to cycle jitter
• 16-pin SOIC package
Applications
• High-resolution VGA controllers
• LCD panels and monitors
• Printers and MFPs
Benefits
• Peak EMI reduction by 8 to 16 dB
• Fast time to market
• Cost reduction
Pin Configuration
REFOFF
2
XIN/CLKIN
3
REFOUT
Loop
Filter
vco
SSCLK1a
DIVIDER
&
8
SSCLK1a
MUX
9
SSCLK1b
/2
15
SSCLK2
•
San Jose
CY25566
1
16
XOUT
REFOFF
2
15
SSCLK2
REFOUT
3
14
VSS
VDD
4
13
S0
VSS
5
12
S1
S2
6
11
VSS
S3
7
10
SSCC
8
9
SSCLK1b
•
CA 95134
•
408-943-2600
Revised October 26, 2005
[+] Feedback

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the CY25566 and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for Cypress Semiconductor CY25566

Summary of Contents for Cypress Semiconductor CY25566

  • Page 1: Block Diagram

    DIVIDER DIVIDER & SSCLK1a SSCLK1b 20 K SSCLK2 RANGE CONTROL 20 K • 3901 North First Street • San Jose CY25566 XIN/CLKIN XOUT REFOFF SSCLK2 REFOUT SSCC SSCLK1a SSCLK1b • CA 95134 • 408-943-2600 Revised October 26, 2005 [+] Feedback...
  • Page 2 Pin Description Name Type XIN/CLKIN Clock or Crystal connection input. Refer to Table 1, Table 2, and Table 3 for input frequency range selection. REFOFF Input pin enables REFOUT clock at pin 3. REFOFF 400KΩ internal pull-up resistor. Logic “0” enables REFOUT, logic “1” disables REFOUT. Default = disabled.
  • Page 3 S0 and S1 are used to program the frequency range and bandwidth of the modulated output clocks SSCLK1a/b and SSCLK2. S0 and S1 of the CY25566 are designed to sense three different analog levels. With this tri-level structure, the CY25566 is able to detect 9 different logic states. Refer to tables 5, 6 and 7 for the results of each of these 9 states.
  • Page 4 Modulation Profile Document #: 38-07429 Rev. *B utilize frequency The CY25566 has three frequency groups to select from. Each combination of frequency and bandwidth can be selected by programming the input control lines, S0–S3, to the proper logic state. Group 1 is the 1X low-frequency range and operates from 25 to 100 MHz.
  • Page 5 S1 = M S0 = 1 S0 = 1 S1 = M S1 = 1 S1 = 0 S1 = 0 S0 = 0 S0 = 0 S0 = 0 S0 = M CY25566 Page 5 of 9 [+] Feedback...

  • Page 6: Application Schematic

    Application Schematic In this example, the CY25566 is being driven by a 75-MHz reference clock. S0 = 0 and S1 = 0 are programmed to select a BW of 2.5%. (Refer to Table 1 and 2.) S2 = 0 and S3 = 1 are programmed to select the Group 2 range.

  • Page 7: Absolute Maximum Ratings

    Power Supply Current Power Supply Current Power Supply Current Table 5. Electrical Timing Characteristics V Duty@1.5V Parameter Description Input Clock Frequency Range Non-crystal, 3.0V Pk–Pk ext. source CLKFR Clock Rise Time RISE(a) Clock Fall Time FALL(a) Clock Rise Time RISE(a+b)

  • Page 8: Ordering Information

    0.150[3.810] 0.157[3.987] 0.230[5.842] 0.244[6.197] S16.15 STANDARD PKG. SZ16.15 LEAD FREE PKG. SEATING PLANE 0.061[1.549] 0.068[1.727] 0.004[0.102] 0°~8° 0.004[0.102] 0.0098[0.249] CY25566 Product Flow MAX. PART # 0.010[0.254] X 45° 0.016[0.406] 0.0075[0.190] 0.016[0.406] 0.0098[0.249] 0.035[0.889] 51-85068-*B Page 8 of 9 [+] Feedback...
  • Page 9 Document Title:CY25566 Spread Spectrum Clock Generator Document Number: 38-07429 Issue Rev. ECN No. Date 115771 07/01/02 122705 12/30/02 404070 See ECN Document #: 38-07429 Rev. *B Orig. of Description of Change Change New Data Sheet Added power up requirements to maximum ratings information.

Table of Contents