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Features
• 3.3V operation
• 48- and 66-MHz frequency support
• Selectable slew rate control
• 350-pS jitter
2
• I
C programmability
• 500- A power-down current
• Spread Spectrum for best electromagnetic interference
(EMI) reduction
• 8-pin SOIC package
Block Diagram
Clock Input
Freq.
Divider
M
SDATA
Logic
SCLOCK
Control
PWRDWN#
Pin Configuration
Cypress Semiconductor Corporation
Document #: 38-07531 Rev. **
CK-SSC Spread Spectrum Clock Generator
VDD
Phase
Charge
Detector
Pump
Modulating
Waveform
Feedback
Divider
N
GND
C L K IN
1
2
V D D
C Y 2 5 8 2 2 -2
3
G N D
C L K O U T
4
* 1 5 0 K
P u ll-u p
•
3901 North First Street
Post
VCO
Dividers
PLL
8
*P W R D W N #
7
S C L O C K
S D A T A
6
5
R E F O U T
,
•
San Jose
CA 95134
CY25822-2
REFOUT
CLKOUT
(SSCG Output)
•
408-943-2600
Revised March 18, 2003
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Related Manuals for Cypress Semiconductor CY25822-2
Summary of Contents for Cypress Semiconductor CY25822-2
- Page 1 S D A T A G N D R E F O U T * 1 5 0 K P u ll-u p • 3901 North First Street • CY25822-2 REFOUT CLKOUT Post (SSCG Output) Dividers San Jose CA 95134 •...
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Page 2: Pin Description
PWRDWN# Output Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions such as individual clock output buffers, etc., can be individually enabled or disabled. - Page 3 (Applies only in Power Down State) Spread Spectrum enable 0 = spread off, 1 = spread on No Pins Spread Mode Down Down Down Down Down CY25822-2 Byte Read Protocol Description Spread Amount% 1.25 1.75 Page 3 of 9 [+] Feedback...
- Page 4 Pin Description an asynchronous active LOW input. This signal is synchro- nized internally to the device powering down the clock synthe- sizer. PWRDWN# is an asynchronous function for powering up the system. When PWRDWN# is low, all clocks are driven to a LOW value and held there and the VCO and PLLs are also powered down.
- Page 5 CLKOUT and REFOUT clocks individually. The VCO and crystal oscillator must remain on. A shutdown clock is driven low. ALL clocks need to be stopped in a predictable manner. All clocks need to be shutdown without any glitches or other abnormal behavior while transitioning to a stopped state.
- Page 6 6.85 Measured @0.4V 5.95 Measured from 0.4V to 2.4V REFOUT and CLOCKOUT Measured from 2.4V to 0.4V REFOUT and CLOCKOUT Measured from 0.4V to 2.4V 1.33 REFOUT and CLOCKOUT CY25822-2 Min. Max. Unit –0.5 –0.5 –0.5 + 0.5 –65 +150 °C...
- Page 7 – times and CLOCKOUT when SSCG is Off From VDD = 2.0 V – Package Type 8-pin SOIC 8-pin SOIC – Tape and Reel CY25822-2 Max. Unit Notes V/ns Low Buffer Strength Refer to I C Control High Buffer Strength...
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Page 8: Package Diagram
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 8-lead (150-Mil) SOIC – S8 C system, provided that the system conforms to the I CY25822-2 51-85066-*B C Standard Specification... - Page 9 CY25822-2 Document History Page Document Title: CY25822-2 CK-SSC Spread Spectrum Clock Generator Document Number: 38-07531 Issue Orig. of REV. ECN NO. Date Change Description of Change 124462 03/19/03 New Data Sheet Document #: 38-07531 Rev. ** Page 9 of 9...
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