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Features
■
All outputs skew <100 ps typical (250 max.)
■
15 to 80 MHz output operation
■
Zero input to output delay
■
50% duty cycle outputs
■
Outputs drive 50Ω terminated lines
■
Low operating current
■
24-pin SOIC package
■
Jitter:<200 ps peak to peak, <25 ps RMS
Functional Description
The CY7B9910 and CY7B9920 Low Skew Clock Buffers offer
low skew system clock distribution. These multiple output clock
drivers optimize the timing of high performance computer
systems. Each of the eight individual drivers can drive terminated
transmission lines with impedances as low as 50Ω. They deliver
minimal and specified output skews and full swing logic levels
(CY7B9910 TTL or CY7B9920 CMOS).
Logic Block Diagram
Cypress Semiconductor Corporation
Document Number: 38-07135 Rev. *B
TEST
PHASE
FB
FREQ
FILTER
DET
REF
FS
•
198 Champion Court
Low Skew Clock Buffer
The completely integrated PLL enables "zero delay" capability.
External divide capability, combined with the internal PLL, allows
distribution of a low frequency clock that is multiplied by virtually
any factor at the clock destination. This facility minimizes clock
distribution difficulty while allowing maximum system clock
speed and flexibility.
Block Diagram Description
Phase Frequency Detector and Filter
The Phase Frequency Detector and Filter blocks accept inputs
from the reference frequency (REF) input and the feedback (FB)
input and generate correction information to control the
frequency of the Voltage Controlled Oscillator (VCO). These
blocks, along with the VCO, form a Phase Locked Loop (PLL)
that tracks the incoming REF signal.
VCO
The VCO accepts analog control inputs from the PLL filter block
and generates a frequency. The operational range of the VCO is
determined by the FS control pin.
VOLTAGE
CONTROLLED
OSCILLATOR
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
,
•
San Jose
CA 95134-1709
CY7B9910
CY7B9920
•
408-943-2600
Revised August 07, 2007
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Table of Contents
Related Manuals for Cypress Semiconductor CY7B9910
Summary of Contents for Cypress Semiconductor CY7B9910
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Page 1: Functional Description
■ Jitter:<200 ps peak to peak, <25 ps RMS Functional Description The CY7B9910 and CY7B9920 Low Skew Clock Buffers offer low skew system clock distribution. These multiple output clock drivers optimize the timing of high performance computer systems. Each of the eight individual drivers can drive terminated transmission lines with impedances as low as 50Ω. -
Page 2: Pin Configuration
Power supply for internal circuitry. Ground. Test Mode The TEST input is a three level input. In normal system operation, this pin is connected to ground, allowing the CY7B9910 and CY7B9920 to operate as described in Block Diagram removable jumper to ground or be tied LOW through a 100W resistor. This enables an external tester to change the state of these pins. -
Page 3: Maximum Ratings
(MIL-STD-883, Method 3015) Latch Up Current ... >200 mA ° ° Operating Range C to +150 ° ° C to +125 Range Commercial Industrial CY7B9910 CY7B9920 Ambient Temperature ° ° 5V ± 10% C to +70 ° ° 5V ± 10% –40... -
Page 4: Electrical Characteristics
5. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. CY7B9920 outputs are not short circuit protected. 6. Total output current per output pair is approximated by the following expression that includes device current plus load current: CY7B9910: ICCN = [(4 + 0.11F) + [((835 – 3F)/Z) + (.0022FC)]N] x 1.1 CY7B9920: ICCN = [(3.5+.17F) + [((1160 –... -
Page 5: Switching Characteristics
Input Capacitance AC Test Loads and Waveforms R1=130 R2=91 = 50 pF (C (Includes fixture and probe capacitance) 7B9910–3 TTL AC Test Load (CY7B9910) R1=100 R2=100 = 50 pF (C (Includes fixture and probe capacitance) 7B9910–5 CMOS AC Test Load (CY7B9920) - Page 6 10. Applies to REF and FB inputs only. 11. Test measurement levels for the CY7B9910 are TTL levels (1.5V to 1.5V). Test measurement levels for the CY7B9920 are CMOS levels (VCC/2 to VCC/2). Test conditions assume signal transition times of 2ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified.
- Page 7 17, 18] Output Fall Time OFALL [19] PLL Lock Time LOCK Cycle-to-Cycle Output Jitter Document Number: 38-07135 Rev. *B CY7B9910–7 [1, 2] FS = LOW [1, 2] FS = MID 1, 2, 3] FS = HIGH [13, 14] –0.7 [16] –1.2...
- Page 8 AC Timing Diagrams OTHER Q Figure 2. Zero Skew and Zero Delay Clock Driver SYSTEM CLOCK TEST Document Number: 38-07135 Rev. *B Figure 1. AC Timing Diagrams RPWL RPWH ODCV ODCV SKEW SKEW CY7B9910 CY7B9920 LOAD LOAD LOAD LOAD Page 8 of 11...
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Page 9: Operational Mode Descriptions
TEST Document Number: 38-07135 Rev. *B Figure 1 shows the CY7B9910/9920 connected in series to construct a zero skew clock distribution tree between boards. Cascaded clock buffers accumulates low frequency jitter because of the non-ideal filtering characteristics of the PLL filter. -
Page 10: Ordering Information
Ordering Information Accuracy Ordering Code (ps) CY7B9910–2SC CY7B9910–2SCT [20] CY7B9920–2SC CY7B9910–5SC CY7B9910–5SCT CY7B9910–5SI CY7B9910–5SIT CY7B9920–5SC CY7B9920–5SCT CY7B9920–5SI CY7B9910–7SC [20] CY7B9910–7SI [20] CY7B9920–7SC [20] CY7B9920–7SI Pb-Free CY7B9910–2SXC CY7B9910–2SXCT CY7B9910–5SXC CY7B9910–5SXCT CY7B9910–5SXI CY7B9910–5SXIT CY7B9910–7SXC CY7B9910–7SXCT Package Diagram Figure 4. 24-Pin (300 Mil) Molded SOIC S13 Note 20. -
Page 11: Document History
Document History Document Title: CY7B9910/CY7B9920 Low Skew Clock Buffer Document Number: 38-07135 Orig. of REV. ECN NO. Issue Date Change 110244 10/28/01 1199925 See ECN DPF/AESA Added Pb-free parts in Ordering Information 1353343 See ECN AESA © Cypress Semiconductor Corporation, 2001-2007.The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product.
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