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Cypress Semiconductor CY2291 Specification Sheet

Cypress three-pll general purpose eprom programmable clock generator specification sheet
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Features
■
Three integrated phase-locked loops
■
EPROM programmability
■
Factory-programmable (CY2291) or field-programmable
(CY2291F) device options
■
Low-skew, low-jitter, high-accuracy outputs
■
Power-management options (Shutdown, OE, Suspend)
■
Frequency select option
■
Smooth slewing on CPUCLK
■
Configurable 3.3V or 5V operation
■
20-pin SOIC Package
Part Number Outputs
CY2291
8
10 MHz–25 MHz (external crystal)
1 MHz–30 MHz (reference clock)
CY2291I
8
10 MHz–25 MHz (external crystal)
1 MHz–30 MHz (reference clock)
CY2291F
8
10 MHz–25 MHz (external crystal)
1 MHz–30 MHz (reference clock)
CY2291FI
8
10 MHz–25 MHz (external crystal)
1 MHz–30 MHz (reference clock)
Logic Block Diagram
S2/SUSPEND
SHUTDOWN/
Cypress Semiconductor Corporation
Document #: 38-07189 Rev. *C
Input Frequency Range
32XIN
OSC.
32XOUT
XTALIN
OSC.
XTALOUT
CPLL
(8 BIT)
S0
S1
UPLL
(10 BIT)
SPLL
(8 BIT)
OE
•
198 Champion Court
Three-PLL General Purpose EPROM
Programmable Clock Generator
Benefits
■
Generates up to three custom frequencies from external
sources
■
Easy customization and fast turnaround
■
Programming support available for all opportunities
■
Meets critical industry standard timing requirements
■
Supports low-power applications
■
Eight user-selectable frequencies on CPU PLL
■
Allows downstream PLLs to stay locked on CPUCLK output
■
Enables application compatibility
■
Industry-standard packaging saves on board space
Output Frequency Range
76.923 kHz–100 MHz (5V)
76.923 kHz–80 MHz (3.3V)
76.923 kHz–90 MHz (5V)
76.923 kHz–66.6 MHz (3.3V)
76.923 kHz–90 MHz (5V)
76.923 kHz–66.6 MHz (3.3V)
76.923 kHz–80 MHz (5V)
76.923 kHz–60.0 MHz (3.3V)
/1,2,4
/1,2,4,8
/1,2,3,4,5,6
/8,10,12,13
/20,24,26,40
/48,52,96,104
/2,3,4
CONFIG
EPROM
,
•
San Jose
CA 95134-1709
CY2291
Specifics
Factory Programmable
Commercial Temperature
Factory Programmable
Industrial Temperature
Field Programmable
Commercial Temperature
Field Programmable
Industrial Temperature
32K
XBUF
CPUCLK
CLKA
CLKB
CLKC
CLKD
CLKF
•
408-943-2600
Revised September 16, 2008
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Summary of Contents for Cypress Semiconductor CY2291

  • Page 1 Features ■ Three integrated phase-locked loops ■ EPROM programmability ■ Factory-programmable (CY2291) or field-programmable (CY2291F) device options ■ Low-skew, low-jitter, high-accuracy outputs ■ Power-management options (Shutdown, OE, Suspend) ■ Frequency select option ■ Smooth slewing on CPUCLK ■ Configurable 3.3V or 5V operation ■...
  • Page 2 3. Please refer to application note “Understanding the CY2291, CY2292 and CY2295” for more information. 4. The CY2291 has weak pull downs on all outputs (except 32K). Hence, when a three-state condition is forced on the outputs, the output pins are pulled LOW.

  • Page 3: Operation

    (<500 ps) skew, in effect providing on-chip buffering for heavily loaded signals. The CY2291 can be configured for either 5V or 3.3V operation. The internal ROM tables use EPROM technology, allowing full customization of output frequencies. The reference oscillator has been designed for 10 MHz to 25 MHz crystals, providing additional flexibility.
  • Page 4 6. External input reference clock must have a duty cycle between 40% and 60%, measured at V 7. Please refer to application note “Crystal Oscillator Topics” for information on AC-coupling the external input reference clock. 8. The oscillator circuit is optimized for a crystal reference and for external reference clocks up to 20 MHz. For external reference clocks above 20 MHz, it is recommended that a 150Ω...
  • Page 5 = 0.5 mA = 0.5 mA Except crystal pins Except crystal pins –0.5V = +0.5V Three-state outputs Max., 3.3V operation Shutdown active, CY2291/CY2291F excluding V BATT = 3.0V BATT Conditions = 4.0 mA = 4.0 mA = 0.5 mA = 0.5 mA...
  • Page 6 Except crystal pins –0.5V = +0.5V Three-state outputs max., 3.3V operation Shutdown active, CY2291I/CY2291FI excluding V BATT = 3.0V BATT Description CY2291 CY2291F ÷ t [12] ÷ t [12] [13] [13] Max. – t min.),% of < 4 MHz) Max. – t min.)
  • Page 7 Lock Time from Power Up CPLL Lock Time for Lock Time from Power Up UPLL and SPLL Slew Limits CPU PLL Slew Limits Document #: 38-07189 Rev. *C (continued) Description CY2291 CY2291F Description CY2291 CY2291F ÷ t [12] ÷ t [12] [13] [13] Max.
  • Page 8 Max. – t min.) (4 MHz < 50 MHz) CY2291I CY2291FI Description CY2291I CY2291FI ÷ t [12] ÷ t [12] [13] [13] CY2291 Min. Typ. Max. Unit 11.1 13000 (90 MHz) (76.923 kHz) 12.5 13000 (80 MHz) (76.923 kHz) < 0.25 20.0...
  • Page 9 < 4 MHz) Max. – t min.) (4 MHz < 50 MHz) > 50 MHz) CY2291I CY2291FI Figure 3. Output Three-State Timing Figure 4. CLK Outputs Jitter and Skew CY2291 Min. Typ. Max. Unit < 0.25 20.0 MHz/ms < 0.5 <...
  • Page 10 & t OUTPUTS Package Type Industrial Commercial Commercial Commercial Commercial Commercial Commercial θ θ (C/W) (C/W) CY2291 CLK out LOAD Operating Range Operating Voltage 3.3V or 5.0V 5.0V 5.0V 3.3V 3.3V 3.3V or 5.0V 3.3V or 5.0V Transistor Count 9271...

  • Page 11: Package Diagram

    CY2291 Package Diagram Figure 6. 20-Pin (300 MIL) SOIC Package Outline 51-85024 *C Document #: 38-07189 Rev. *C Page 11 of 12 [+] Feedback...
  • Page 12 Document History Page Document Title: CY2291 Three-PLL General Purpose EPROM Programmable Clock Generator Document Number: 38-07189 Orig. of Submission REV. Change 110321 121836 276756 2565316 AESA/KVM Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.