Cypress Semiconductor CY7C144 Specification Sheet

CY7C144 CY7C1458K x 8/9 Dual-Port Static RAM
with SEM, INT, BUSY
Features
True Dual-Ported memory cells that enable simultaneous
■
reads of the same memory location
8K x 8 organization (CY7C144)
■
8K x 9 organization (CY7C145)
■
0.65-micron CMOS for optimum speed and power
■
High speed access: 15 ns
■
Low operating power: I
■
CC
Fully asynchronous operation
■
Automatic power down
■
TTL compatible
■
Master/Slave select pin enables bus width expansion to
■
16/18 bits or more
Busy arbitration scheme provided
■
Semaphores included to permit software handshaking
■
between ports
INT flag for port-to-port communication
■
Available in 68-pin PLCC, 64-pin and 80-pin TQFP
■
Pb-free packages available
■
Logic Block Diagram
Notes
1. BUSY is an output in master mode and an input in slave mode.
2. Interrupt: push-pull output and requires no pull-up resistor.
Cypress Semiconductor Corporation
Document #: 38-06034 Rev. *D
= 160 mA (max.)
R/ W L
CE L
OE L
(7C145) I /O 8L
I /O7L
I / O 0L
[1, 2]
B US Y L
A 12L
ADDRE SS
A 0L
DE CODE R
CE L
OE L
R/ W L
SE M L
[ 2]
I NT L
• 198 Champion Court
8K x 8/9 Dual-Port Static RAM
with SEM, INT, BUSY

Functional Description

The CY7C144 and CY7C145 are high speed CMOS 8K x 8
and 8K x 9 dual-port static RAMs. Various arbitration schemes
are included on the CY7C144/5 to handle situations when
multiple processors access the same piece of data. Two ports
are provided permitting independent, asynchronous access
for reads and writes to any location in memory. The
CY7C144/5 can be used as a standalone 64/72-Kbit dual-port
static RAM or multiple devices can be combined in order to
function as a 16/18-bit or wider master/slave dual-port static
RAM. An M/S pin is provided for implementing 16/18-bit or
wider memory applications without the need for separate
master and slave devices or additional discrete logic. Appli-
cation areas include interprocessor/multiprocessor designs,
communications status
video/graphics memory.
Each port has independent control pins: chip enable (CE),
read or write enable (R/W), and output enable (OE). Two flags,
BUSY and INT, are provided on each port. BUSY signals that
the port is trying to access the same location currently being
accessed by the other port. The interrupt flag (INT) permits
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from
one port to the other to indicate that a shared resource is in
use. The semaphore logic is comprised of eight shared
latches. Only one side can control the latch (semaphore) at
any time. Control of a semaphore indicates that a shared
resource is in use. An automatic power down feature is
controlled independently on each port by a chip enable (CE)
pin or SEM pin.
I/ O
I /O
CONT ROL CONT ROL
M EM ORY
A DDRES S
A RRA Y
DECODE R
INT ERRUP T
SE MA P HORE
CE R
ARB I TRAT IO N
OE R
R/W R
M /S
,
• San Jose
CY7C145, CY7C144
buffering, and
R/ W R
CE R
OE R
I/ O 8R (7C14 5)
I/ O 7R
I/ O 0R
[ 1, 2]
BUS Y R
A 12R
A 0R
SE M R
I NT R [ 2]
CA 95134-1709 • 408-943-2600
Revised December 10, 2008
dual-port
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