Cypress Semiconductor CY7C1360C Specification Sheet

Features
• Supports bus operation up to 250 MHz
• Available speed grades are 250, 200, and 166 MHz
• Registered inputs and outputs for pipelined operation
• 3.3V core power supply (V
• 2.5V/3.3V I/O operation (V
• Fast clock-to-output times
— 2.8 ns (for 250-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel
®
Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Single Cycle Chip Deselect
• Available in lead-free 100-Pin TQFP package, lead-free
and non lead-free 119-Ball BGA package and 165-Ball
FBGA package
• TQFP Available with 3-Chip Enable and 2-Chip Enable
• IEEE 1149.1 JTAG-Compatible Boundary Scan
Logic Block Diagram – CY7C1362C (512K x 18)
ADDRESS
A0, A1, A
REGISTER
MODE
ADV
CLK
ADSC
ADSP
DQ
WRITE REGISTER
BW
B
DQ
BW WRITE REGISTER
A
BWE
GW
ENABLE
CE
1
REGISTER
CE2
CE3
OE
SLEEP
ZZ
CONTROL
Notes:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
2. CE is for A version of TQFP (3 Chip Enable option) and 165 FBGA package only. 119 BGA is offered only in 2 Chip Enable.
3
Cypress Semiconductor Corporation
Document #: 38-05540 Rev. *H
9-Mbit (256K x 36/512K x 18) Pipelined SRAM
)
DD
)
DDQ
®
A[1:0]
2
Q1
BURST
COUNTER AND
LOGIC
CLR Q0
DQP
B, B
DQP
A, A
PIPELINED
ENABLE
• 198 Champion Court

Functional Description

The CY7C1360C/CY7C1362C SRAM integrates 256K x 36
and 512K x 18 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining Chip Enable (CE
[2]
Enables (CE and CE
2 3
and ADV), Write Enables (BW
(GW). Asynchronous inputs include the Output Enable (OE)
and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two or four bytes wide as
controlled by the Byte Write control inputs. GW when active
LOW cause s all bytes to be written.
The CY7C1360C/CY7C1362C operates from a +3.3V core
power supply while all outputs may operate with either a +2.5
or +3.3V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
DQ DQP
B, B
WRITE DRIVER
SENSE
MEMORY
AMPS
ARRAY
DQ DQP
A, A
WRITE DRIVER
,
• San Jose CA 95134-1709
CY7C1360C
CY7C1362C
[1]
), depth-expansion Chip
1
), Burst Control inputs (ADSC, ADSP,
, and BWE), and Global Write
X
OUTPUT
OUTPUT
BUFFERS
REGISTERS
E
INPUT
REGISTERS
• 408-943-2600
Revised September 14, 2006
DQs
DQP
A
DQP
B
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