Cypress Semiconductor MoBL CY62157EV30 Specification Sheet

Features
• TSOP I package configurable as 512K x 16 or as 1M x 8
SRAM
• High speed: 45 ns
• Wide voltage range: 2.20V–3.60V
• Pin compatible with CY62157DV30
• Ultra low standby power
— Typical Standby current: 2 µA
— Maximum Standby current: 8 µA (Industrial)
• Ultra low active power
— Typical active current: 1.8 mA @ f = 1 MHz
• Easy memory expansion with CE
• Automatic power down when deselected
• CMOS for optimum speed and power
• Available in both Pb-free and non Pb-free 48-ball VFBGA,
Pb-free 44-pin TSOP II and 48-pin TSOP I packages
Functional Description
The CY62157EV30 is a high performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
Logic Block Diagram
Power Down
Circuit
Notes
1. For best practice recommendations, please refer to the Cypress application note
Cypress Semiconductor Corporation
Document #: 38-05445 Rev. *E
, CE , and OE features
1 2
[1]
®
) in
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A
512K × 16 / 1M x 8
6
A
RAM Array
5
A
4
A
3
A
2
A
1
A
0
COLUMN DECODER
CE
2
CE
1
BHE
BLE
• 198 Champion Court
CY62157EV30 MoBL
8-Mbit (512K x 16) Static RAM
reduces power consumption when addresses are not toggling.
Place the device into standby mode when deselected (CE
HIGH or CE LOW or both BHE and BLE are HIGH). The input
2
or output pins (IO through IO
0
impedance state when:
• Deselected (CE HIGH or CE
1
• Outputs are disabled (OE HIGH)
• Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
• Write operation is active (CE
LOW)
To write to the device, take Chip Enable (CE
HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from IO pins (IO
written into the location specified on the address pins (A
through A ). If Byte High Enable (BHE) is LOW, then data
18
from IO pins (IO through IO
8
specified on the address pins (A
To read from the device, take Chip Enable (CE
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
appear on IO to IO . If Byte High Enable (BHE) is LOW, then
0 7
data from memory appears on IO
Table" on page 10 for a complete description of read and write
modes.
AN1064, SRAM System Guidelines.
,
• San Jose CA 95134-1709
®
) are placed in a high
15
LOW)
2
LOW, CE HIGH and WE
1 2
LOW and CE
1
through IO ) is
0 7
) is written into the location
15
through A ).
0 18
LOW and CE
1
to IO . See the "Truth
8 15
IO –IO
0 7
IO –IO
8 15
BYTE
BHE
WE
CE
2
CE
1
OE
BLE
• 408-943-2600
Revised May 07, 2007
1
2
0
2
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