Cypress Semiconductor MoBL CY62138F Specification Sheet

2-mbit (256k x 8) static ram

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Features
• High speed: 45 ns
• Wide voltage range: 4.5 V – 5.5 V
• Pin compatible with CY62138V
• Ultra low standby power
— Typical standby current: 1 µA
— Maximum standby current: 5 µA
• Ultra low active power
— Typical active current: 1.6 mA @ f = 1 MHz
• Easy memory expansion with CE
• Automatic power down when deselected
• CMOS for optimum speed and power
• Available in Pb-free 32-pin SOIC and 32-pin TSOP II
packages
Logic Block Diagram
CE 1
CE 2
Note
1. For best practice recommendations, refer to the Cypress application note "System Design Guidelines" at
Cypress Semiconductor Corporation
Document #: 001-13194 Rev. *A
, CE
and OE features
1
2,
DATA IN DRIVERS
A 0
A 1
A 2
A 3
A 4
A 5
256K x 8
A 6
A 7
ARRAY
A 8
A 9
A 10
A 11
COLUMN DECODER
WE
OE
198 Champion Court
2-Mbit (256K x 8) Static RAM

Functional Description

The CY62138F is a high performance CMOS static RAM
organized as 256K words by 8 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption when addresses are not toggling.
Placing the device into standby mode reduces power
consumption by more than 99% when deselected (CE
or CE
LOW).
2
To write to the device, take Chip Enable (CE
HIGH) and Write Enable (WE) inputs LOW. Data on the eight
IO pins (IO
through IO
) is then written into the location
0
7
specified on the address pins (A
To read from the device, take Chip Enable (CE
HIGH) and output enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins appear on
the IO pins.
The eight input and output pins (IO
in a high impedance state when the device is deselected (CE
HIGH or CE
LOW), the outputs are disabled (OE HIGH), or
2
during a write operation (CE
LOW).
POWER
DOWN
http://www.cypress.com.
,
San Jose
CA 95134-1709
CY62138F MoBL
[1]
®
) in
HIGH
1
LOW and CE
1
through A
).
0
17
LOW and CE
1
through IO
) are placed
0
7
LOW and CE
HIGH and WE
1
2
IO 0
IO 1
IO 2
IO 3
IO 4
IO 5
IO 6
IO 7
408-943-2600
Revised March 26, 2007
®
2
2
1
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Summary of Contents for Cypress Semiconductor MoBL CY62138F

  • Page 1: Functional Description

    Features • High speed: 45 ns • Wide voltage range: 4.5 V – 5.5 V • Pin compatible with CY62138V • Ultra low standby power — Typical standby current: 1 µA — Maximum standby current: 5 µA • Ultra low active power —...
  • Page 2: Pin Configuration

    Pin Configuration Product Portfolio Range (V) Product CY62138FLL 4.5V 5.0V Notes 2. NC pins are not connected on the die. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V Document #: 001-13194 Rev.
  • Page 3: Maximum Ratings

    Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ... –65°C to + 150°C Ambient Temperature with Power Applied ... –55°C to + 125°C Supply Voltage to Ground Potential ...–0.5V to 6.0V (V DC Voltage Applied to Outputs [4, 5]...
  • Page 4 AC Test Loads and Waveforms OUTPUT 30 pF INCLUDING JIG AND Equivalent to: SCOPE Parameters Data Retention Characteristics Parameter Description for Data Retention Data Retention Current CCDR Chip Deselect to Data Retention Time Operation Recovery Time [10] Data Retention Waveform Notes: 9.
  • Page 5: Switching Characteristics

    Switching Characteristics (Over the Operating Range) Parameter Read Cycle Read Cycle Time Address to Data Valid Data Hold from Address Change LOW and CE OE LOW to Data Valid OE LOW to Low-Z LZOE OE HIGH to High-Z HZOE LOW and CE LZCE HIGH or CE HZCE...
  • Page 6: Switching Waveforms

    Switching Waveforms Read Cycle 1 (Address transition controlled) ADDRESS DATA OUT PREVIOUS DATA VALID [10, 16, 17] Read Cycle No. 2 (OE controlled) ADDRESS LZOE HIGH IMPEDANCE DATA OUT LZCE SUPPLY CURRENT [10, 14, 18, 19] Write Cycle No. 1 (WE controlled) ADDRESS NOTE 20 DATA IO...
  • Page 7: Ordering Information

    Switching Waveforms (continued) Write Cycle No. 2 (CE1 or CE2 controlled) ADDRESS DATA IO Write Cycle No. 3 (WE controlled, OE LOW) ADDRESS NOTE 20 DATA IO HZWE Truth Table Inputs/Outputs High Z Data Out Data In High Z Ordering Information Speed (ns) Ordering Code...
  • Page 8: Package Diagrams

    Package Diagrams Figure 1. 32-pin (450 Mil) Molded SOIC, 51-85081 0.793[20.142] 0.817[20.751] 0.101[2.565] 0.111[2.819] 0.050[1.270] BSC. 0.014[0.355] 0.020[0.508] Document #: 001-13194 Rev. *A 0.546[13.868] 0.566[14.376] 0.440[11.176] 0.450[11.430] 0.006[0.152] 0.012[0.304] 0.118[2.997] MAX. 0.004[0.102] 0.004[0.102] MIN. SEATING PLANE ® CY62138F MoBL 0.047[1.193] 0.063[1.600] 0.023[0.584] 0.039[0.990]...
  • Page 9 Package Diagrams (continued) Figure 2. 32-Pin TSOP II, 51-85095 MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 001-13194 Rev.
  • Page 10 Document History Page ® Document Title: CY62138F MoBL 2-Mbit (256K x 8) Static RAM Document Number: 001-13194 Orig. of REV. ECN NO. Issue Date Change 797956 See ECN 940341 See ECN Document #: 001-13194 Rev. *A Description of Change New Data Sheet Added footnote #7 related to I ®...

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