Cypress Semiconductor Perform CY62136EV30 Specification Sheet

Features
• Very high speed: 45 ns
• Wide voltage range: 2.20V–3.60V
• Pin-compatible with CY62136CV30
• Ultra low standby power
— Typical standby current: 1µA
— Maximum standby current: 7µA
• Ultra-low active power
— Typical active current: 2 mA @ f = 1 MHz
• Easy memory expansion with CE, and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Offered in a Pb-free 48-ball VFBGA and 44-pin TSOP II
packages
Logic Block Diagram
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Note:
1. For best practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05569 Rev. *B
2-Mbit (128K x 16) Static RAM
Functional Description
The CY62136EV30 is a high-performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption by 80% when addresses are not
toggling. The device can also be put into standby mode
reducing power consumption by more than 99% when
deselected (CE HIGH). The input/output pins (I/O
I/O
15
(CE HIGH), outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH),
or during a write operation (CE LOW and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
written into the location specified on the address pins (A
through A
from I/O pins (I/O
specified on the address pins (A
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
LOW, then data from memory will appear on I/O
the truth table at the back of this data sheet for a complete
description of read and write modes.
DATA IN DRIVERS
128K x 16
RAM Array
COLUMN DECODER
• 198 Champion Court
[1]
) are placed in a high-impedance state when: deselected
). If Byte High Enable (BHE) is LOW, then data
16
through I/O ) is written into the location
8 15
through A
0
to I/O . If Byte High Enable (BHE) is
0 7
I/O –I/O
0 7
I/O –I/O
8 15
BHE
WE
CE
OE
BLE
,
• San Jose CA 95134-1709
Revised January 6, 2006
CY62136EV30
®
MoBL
®
) in
through
0
through I/O ), is
0 7
0
).
16
to I/O . See
8 15
• 408-943-2600
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