Cypress Semiconductor CY62157CV30 Specification Sheet

Features
• Temperature Ranges
— Automotive-A: –40°C to 85°C
— Automotive-E: –40°C to 125°C
• Voltage range:
— CY62157CV30: 2.7V–3.3V
— CY62157CV33: 3.0V–3.6V
• Ultra-low active power
— Typical active current: 1.5 mA @ f = 1 MHz
— Typical active current: 5.5 mA @ f = f
• Low standby power
• Easy memory expansion with CE
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Available in Pb-free and non Pb-free 48-ball FBGA
package
Functional Description
The CY62157CV30/33 are high-performance CMOS static
RAMs organized as 512K words by 16 bits. These devices
feature advanced circuit design to provide ultra-low active
current. This is ideal for providing More Battery Life™
(MoBL™) in portable applications such as cellular telephones.
The devices also have an automatic power-down feature that
Logic Block Diagram
Note:
1. For best practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05014 Rev. *F
max
, CE and OE features
1 2
[1]
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A
512K × 16
6
A
RAM Array
5
A
4
A
3
A
2
A
1
A
0
COLUMN DECODER
Power -down
Circuit
• 198 Champion Court
512K x 16 Static RAM
significantly reduces power consumption by 80% when
addresses are not toggling. The device can also be put into
standby mode reducing power consumption by more than 99%
when deselected (CE HIGH or CE
1
BHE are HIGH). The input/output pins (I/O
placed in a high-impedance state when: deselected (CE
HIGH or CE LOW), outputs are disabled (OE HIGH), both
2
Byte High Enable and Byte Low Enable are disabled (BHE,
BLE HIGH), or during a write operation (CE
HIGH and WE LOW).
Writing to the device is accomplished by taking Chip Enable 1
(CE ) and Write Enable (WE) inputs LOW and Chip Enable 2
1
(CE ) HIGH. If Byte Low Enable (BLE) is LOW, then data from
2
I/O pins (I/O through I/O
0 7
specified on the address pins (A
Enable (BHE) is LOW, then data from I/O pins (I/O
I/O ) is written into the location specified on the address pins
15
(A through A ).
0 18
Reading from the device is accomplished by taking Chip
Enable 1 (CE ) and Output Enable (OE) LOW and Chip
1
Enable 2 (CE ) HIGH while forcing the Write Enable (WE)
2
HIGH. If Byte Low Enable (BLE) is LOW, then data from the
memory location specified by the address pins will appear on
I/O to I/O . If Byte High Enable (BHE) is LOW, then data from
0 7
memory will appear on I/O to I/O
8
back of this data sheet for a complete description of read and
write modes.
The CY62157CV30/33 are available in a 48-ball FBGA
package.
I/O –I/O
0 7
I/O –I/O
8 15
BHE
WE
OE
BLE
CE
BHE
CE
BLE
,
• San Jose CA 95134-1709
CY62157CV30/33
LOW or both BLE and
2
through I/O ) are
0 15
LOW and CE
1
), is written into the location
through A ). If Byte High
0 18
through
8
. See the truth table at the
15
CE
2
CE
1
2
1
• 408-943-2600
Revised August 31, 2006
1
2
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