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Features
■
Powerful Harvard Architecture Processor
❐
M8C Processor Speeds to 24 MHz
❐
8x8 Multiply, 32-Bit Accumulate
❐
Low Power at High Speed
❐
2.4 to 5.25V Operating Voltage
❐
Operating Voltages Down to 1.0V Using On-Chip Switch
Mode Pump (SMP)
❐
Industrial Temperature Range: -40°C to +85°C
■
Advanced Peripherals (PSoC Blocks)
❐
Six Rail-to-Rail Analog PSoC Blocks Provide:
• Up to 14-Bit ADCs
• Up to 9-Bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
❐
Four Digital PSoC Blocks Provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
• Full-Duplex UART
• Multiple SPI™ Masters or Slaves
• Connectable to All GPIO Pins
❐
Complex Peripherals by Combining Blocks
■
Precision, Programmable Clocking
❐
Internal ±2.5% 24/48 MHz Oscillator
❐
High accuracy 24 MHz with optional 32 kHz Crystal and PLL
❐
Optional External Oscillator, up to 24 MHz
❐
Internal Oscillator for Watchdog and Sleep
■
Flexible On-Chip Memory
❐
4K Flash Program Storage 50,000 Erase/Write Cycles
❐
256 Bytes SRAM Data Storage
❐
In-System Serial Programming (ISSP)
❐
Partial Flash Updates
❐
Flexible Protection Modes
❐
EEPROM Emulation in Flash
■
Programmable Pin Configurations
❐
25 mA Sink on all GPIO
❐
Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on All GPIO
❐
Up to Ten Analog Inputs on GPIO
❐
Two 30 mA Analog Outputs on GPIO
❐
Configurable Interrupt on All GPIO
Cypress Semiconductor Corporation
Document Number: 38-12028 Rev. *I
®
PSoC
Programmable System-on-Chip™
■
New CY8C24x23A PSoC Device
❐
Derived From the CY8C24x23 Device
❐
Low Power and Low Voltage (2.4V)
■
Additional System Resources
❐
I
❐
Watchdog and Sleep Timers
❐
User-Configurable Low Voltage Detection
❐
Integrated Supervisory Circuit
❐
On-Chip Precision Voltage Reference
■
Complete Development Tools
❐
Free Development Software (PSoC Designer™)
❐
Full-Featured, In-Circuit Emulator, and Programmer
❐
Full Speed Emulation
❐
Complex Breakpoint Structure
❐
128K Trace Memory
Logic Block Diagram
•
198 Champion Court
CY8C24223A, CY8C24423A
2
C™ Slave, Master, and MultiMaster to 400 kHz
Port 2 Port 1 Port 0
PSoC CORE
System Bus
Global Digital Interconnect
SRAM
SROM
Flash 4K
256 Bytes
CPU Core (M8C)
Interrupt
Controller
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
ANALOG SYSTEM
Digital
Analog
Block
Array
Digital
Multiply
POR and LVD
2
Decimator
I
C
Clocks
Accum.
System Resets
SYSTEM RESOURCES
,
•
San Jose
CA 95134-1709
CY8C24123A
Analog
Drivers
Global Analog Interconnect
Sleep and
Watchdog
Analog
Ref
Block
Array
Analog
Input
Muxing
Internal
Switch
Voltage
Mode
Ref.
Pump
•
408-943-2600
Revised December 11, 2008
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Table of Contents
Related Manuals for Cypress Semiconductor CY8C24123A
Summary of Contents for Cypress Semiconductor CY8C24123A
- Page 1 Interrupt Controller DIGITAL SYSTEM Digital Multiply Clocks Accum. • 198 Champion Court • San Jose CY8C24123A CY8C24223A, CY8C24423A Analog Port 2 Port 1 Port 0 Drivers Global Analog Interconnect SROM Flash 4K CPU Core (M8C) Sleep and Watchdog Multiple Clock Sources...
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Page 2: Functional Overview
Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This gives a choice of system resources for your application. Family resources are shown in Table 1 on page 4. CY8C24123A Port 0 To Analog System GOE[7:0] GOO[7:0]... -
Page 3: Analog System
ASC10 ASD11 ASD20 ASC21 Analog Reference Interface to Reference RefHi Digital System Generators RefLo AGND M8C Interface (Address Bus, Data Bus, Etc.) CY8C24123A P0[6] P0[4] P0[2] P0[0] P2[6] P2[4] P2[2] P2[0] AGNDIn RefIn Bandgap Page 3 of 56 [+] Feedback... -
Page 4: Getting Started
Design Resources list located in the center of the web page. Application notes are listed by date as default. Bytes Bytes Bytes Bytes Bytes CY8C24123A CY8C24223A, CY8C24423A web site and select Application Notes Page 4 of 56 [+] Feedback... -
Page 5: Development Tools
The embedded, optimizing C compiler provides all the features of C tailored to the PSoC architecture. It comes complete with Device embedded libraries providing port and bus operations, standard Programmer keypad and display support, and extended math functionality. CY8C24123A CY8C24223A, CY8C24423A dynamic reconfiguration. Dynamic Page 5 of 56... -
Page 6: Hardware Tools
User Source Module Code Parameter- Selection Generator ization Generate Application Application Editor Source Project Build Code Manager Manager Editor Build Debugger Event & Interface Storage Breakpoint to ICE Inspector Manager CY8C24123A signal chains by Page 6 of 56 [+] Feedback... -
Page 7: Document Conventions
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal. CY8C24123A Description on page 18. Table 8 on page 14 lists all ‘b’... - Page 8 * These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable Sytem-on-Chip Technical Reference Manual for details. Document Number: 38-12028 Rev. *I CY8C24223A, CY8C24423A Figure 5. CY8C24123A 8-Pin PSoC Device Description A, IO, P0[5]...
- Page 9 Description A, I, P0[7] A, IO, P0[5] A, IO, P0[3] A, I, P0[1] I2C SCL, P1[7] I2C SDA, P1[5] I2C SCL, XTALin, P1[1] CY8C24123A P0[6], A, I P0[4], A, I P0[2], A, I PDIP P0[0], A, I SSOP XRES SOIC...
- Page 10 A, IO, P0[3] A, I, P0[1] A, I, P2[3] A, I, P2[1] I2C SCL, P1[7] I2C SDA, P1[5] I2C SCL, XTALin, P1[1] CY8C24123A P0[6], A, I P0[4], A, I P0[2], A, I P2[7] P0[0], A, I P2[5] P2[6], External VRef...
- Page 11 Figure 9. CY8C24423A 32-Pin Sawn PSoC Device P2[7] P2[5] A, I, P2[3] A, I, P2[1] 12 CS CL, P1[7] 12 CS DA, P1[5] CY8C24123A P0[2], A, I P0[0], A, I P2[6], External VRef P2[4], External AGND P2[2], A, I (Top View )
- Page 12 OCDO P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] I2C SCL, P1[7] I2C SDA, P1[5] P1[3] SCLK, I2C SCL, XTALIn, P1[1] CY8C24123A P0[6], AI P0[4], AIO P0[2], AIO P0[0], AI P2[6], External VRef P2[4], External AGND P2[2], AI P2[0], AI P4[6] P4[4]...
- Page 13 * These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable Sytem-on-Chip Technical Reference Manual for details. Document Number: 38-12028 Rev. *I CY8C24223A, CY8C24423A Description CY8C24123A Page 13 of 56 [+] Feedback...
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Page 14: Register Reference
When the XOI bit is set the user is in Bank 1. Note In the following register mapping tables, blank fields are reserved and must not be accessed. CY8C24123A Page 14 of 56 [+] Feedback... - Page 15 ASD11CR2 ASD11CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 # Access is bit specific. CY8C24123A Addr Access Name Access (0,Hex) I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR3 INT_MSK3 INT_MSK0 INT_MSK1 INT_VC RES_WDT...
- Page 16 ASD11CR2 ASD11CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 # Access is bit specific. CY8C24123A Addr Access Name Access (0,Hex) CPU_SCR1 CPU_SCR0 Addr Access Name Access (1,Hex) GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU OSC_GO_EN...
- Page 17 Blank fields are Reserved and must not be accessed. Document Number: 38-12028 Rev. *I CY8C24223A, CY8C24423A Addr Addr Access Name (1,Hex) (1,Hex) # Access is bit specific. CY8C24123A Addr Access Name Access (1,Hex) CPU_F CPU_SCR1 CPU_SCR0 Page 17 of 56...
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Page 18: Electrical Specifications
≤ 100°C, except where noted. Figure 12. IMO Frequency Trim Options 5.25 4.75 3.60 3.00 2.40 12 MHz 24 MHz 93 kHz Symbol μW CY8C24123A CY8C24223A, CY8C24423A SLIMO SLIMO Mode=1 Mode=0 SLIMO SLIMO Mode=1 Mode=0 SLIMO SLIMO Mode=1 Mode=1... -
Page 19: Absolute Maximum Ratings
– +100 °C The temperature rise from ambient to junction is package specific. See Table 50 limit the power consumption to comply with this requirement. CY8C24123A Notes Notes on page 51. The user must Page 19 of 56 [+] Feedback... -
Page 20: Dc Electrical Characteristics
– – – 1.28 1.30 1.33 1.16 1.30 1.33 CY8C24123A CY8C24223A, CY8C24423A ≤ 85°C, respectively. Typical parameters apply to Units Notes See DC POR and LVD specifications, Table 29 on page 30. Conditions are Vdd = 5.0V, T = 25°C, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz,... - Page 21 – – – – – – CY8C24123A ≤ 85°C, respectively. Typical parameters Notes IOH = 10 mA, Vdd = 4.75 to 5.25V (maximum 40 mA on even port pins (for example, P0[2], P1[4]), maximum 40 mA on odd port pins (for example, P0[3], P1[5])).
- Page 22 1600 – 2400 3200 – 4600 6400 – CY8C24123A ≤ 85°C, respectively. Typical parameters Notes Gross tested to 1 μA Package and pin dependent. Temp = 25°C The common-mode input voltage range is measured through an analog output buffer. The...
- Page 23 μA – μA – μA – 1200 1600 μA – 2400 3200 μA – 4600 6400 Vss ≤ VIN ≤ (Vdd - 2.25) or – (Vdd - 1.25V) ≤ VIN ≤ Vdd CY8C24123A Notes Page 23 of 56 [+] Feedback...
- Page 24 3200 – 4600 6400 ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T – Vdd - 1 – – CY8C24123A CY8C24223A, CY8C24423A Units Notes μV/°C Gross tested to 1 μA – Package and pin dependent. Temp = 25°C The common-mode input voltage range is measured through an analog output buffer.
- Page 25 – – – – 0.5 x Vdd - 1.0 – – 0.5 x Vdd - 1.0 – – CY8C24123A ≤ 85°C, respectively. Typical parameters Units Notes μV/°C > (Vdd - 1.25). Units Notes μV/°C > (Vdd - 1.25) Page 25 of 56...
- Page 26 5.25 3.00 3.25 3.60 2.45 2.55 2.80 – – – – – – – CY8C24123A CY8C24223A, CY8C24423A Units Notes μV/°C – Vdd - 1.0 – – – – 0.5 x Vdd - 0.7 0.5 x Vdd - 0.7 – > (Vdd - 1.25).
- Page 27 – – = Schottky diode. See Figure Figure 13. Basic Switch Mode Pump Circuit Battery PSoC CY8C24123A CY8C24223A, CY8C24423A Units Notes Configuration listed in footnote. is the “Vdd Value for PUMP Trip” specified by the VM[2:0] setting in the DC POR and LVD...
- Page 28 1.6 x BG - 0.027 1.6 x BG - 0.010 -0.034 0.000 Not Allowed Not Allowed Not Allowed Not Allowed CY8C24123A ≤ 85°C, respectively. Typical parameters Units 1.33 Vdd/2 + 0.007 2 x BG + 0.024 P2[4] + 0.011 BG + 0.016 1.6 x BG + 0.018...
- Page 29 P2[4] + P2[6] - 0.01 Not Allowed Not Allowed Not Allowed Not Allowed Not Allowed P2[4] - P2[6] - 0.05 P2[4]- P2[6] + 0.01 CY8C24123A Units P2[4] - P2[6] + 0.092 Units 1.33 Vdd/2 + 0.01 P2[4] + 0.01 BG + 0.015 0.034...
- Page 30 4.54 4.64 4.62 4.73 4.71 4.82 4.89 5.00 (PORLEV=00) for falling supply. (PORLEV=01) for falling supply. CY8C24123A CY8C24223A, CY8C24423A ≤ 85°C, respectively. Typical parameters apply to Units Notes – kΩ – ≤ 85°C, respectively. Typical parameters apply to Units Notes Vdd must be greater than 2.40...
- Page 31 – – Vdd - 1.0 – 50,000 – 1,800,000 – – AN2015 http://www.cypress.com CY8C24123A CY8C24223A, CY8C24423A ≤ 85°C, respectively. Typical parameters apply to Units Notes – – Driving internal pull down resistor. Driving internal pull down resistor. Vss + 0.75 –...
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Page 32: Ac Electrical Characteristics
– – 12.3 – – “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for CY8C24123A CY8C24223A, CY8C24423A ≤ 85°C, respectively. Typical parameters Units Notes MHz Trimmed for 5V or 3.3V operation using factory trim values. See Figure on page 18. - Page 33 – – – – 12.7 μs – – CY8C24123A Notes factory trim values. See Figure 12 page 18. SLIMO mode = 1. factory trim values. See Figure 12 page 18. SLIMO mode = 1. Refer to the AC Digital Block Specifications.
- Page 34 Figure 18. 32 kHz Period Jitter (ECO) Timing Diagram 32K2 Document Number: 38-12028 Rev. *I CY8C24223A, CY8C24423A Figure 14. PLL Lock Timing Diagram PLLSLEW PLLSLEWLOW Jitter24M1 Jitter32k CY8C24123A 24 MHz 24 MHz 32 kHz Page 34 of 56 [+] Feedback...
- Page 35 – Figure 19. GPIO Timing Diagram TRiseF TFallF TRiseS TFallS CY8C24123A ≤ 85°C, respectively. Typical parameters Notes Normal Strong Mode Vdd = 4.5 to 5.25V, 10% - 90% Vdd = 4.5 to 5.25V, 10% - 90% Vdd = 3 to 5.25V, 10% - 90% Vdd = 3 to 5.25V, 10% - 90%...
- Page 36 – – – – – – 0.15 0.01 0.75 – – – – – 0.31 0.24 0.67 – CY8C24123A ≤ 85°C, respectively. Typical parameters Units μs – μs – 0.72 μs – 0.62 μs – μs – 0.92 μs –...
- Page 37 Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Noise at 1 kHz (Power = Medium, Opamp Bias = High) Document Number: 38-12028 Rev. *I CY8C24123A CY8C24223A, CY8C24423A – – 3.92 –...
- Page 38 10000 1000 0.001 Document Number: 38-12028 Rev. *I 0.01 Freq (kHz) Figure 21. Typical Opamp Noise 0.01 Freq (kHz) CY8C24123A CY8C24223A, CY8C24423A 0.01 PH_BH PH_BL PM_BL PL_BL Page 38 of 56 [+] Feedback...
- Page 39 – – – – – – – – – – – CY8C24123A CY8C24223A, CY8C24423A ≤ 85°C, respectively. Typical parameters apply to Units Notes μs ≥ 50 mV overdrive comparator reference set within V REFLPC ≤ 85°C, respectively. Typical parameters Units Notes –...
- Page 40 – – – – 12.7 Maximum data rate at 1.59 MHz due to 8 x over clocking. – – 12.7 Maximum data rate at 1.59 MHz due to 8 x over clocking. CY8C24123A Notes Page 40 of 56 [+] Feedback...
- Page 41 ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T , 3dB BW, 100 pF Load , 3dB BW, 100 pF Load , 3dB BW, 100 pF Load , 3dB BW, 100 pF Load CY8C24123A CY8C24223A, CY8C24423A ≤ 85°C, respectively. Typical parameters – –...
- Page 42 Document Number: 38-12028 Rev. *I , 3dB BW, 100 pF Load , 3dB BW, 100 pF Load ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T 0.093 0.093 0.186 CY8C24123A CY8C24223A, CY8C24423A – – – – – –...
- Page 43 – – – – – – ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T Standard Mode – – – – – – CY8C24123A CY8C24223A, CY8C24423A 0.093 – 12.3 0.186 – 12.3 41.7 – 5300 41.7 – – –...
- Page 44 Standard Mode – – – – – – – – – – SUDATI2C HDSTAI2C SUSTAI2C CY8C24123A CY8C24223A, CY8C24423A Fast Mode Units μs – μs – Š 250 ns must then be met. This is SU;DAT Fast Mode Units – –...
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Page 45: Packaging Information
0.380 0.390 PIN 1 ID DIMENSIONS IN INCHES MIN. 0.240 0.260 0.100 BSC. SEATING PLANE 0.115 0.145 0.008 0.015 MIN. 0.015 0.055 0.070 CY8C24123A CY8C24223A, CY8C24423A MAX. 0.300 0.325 0°-10° 0.430 MAX. 51-85075 *A Page 45 of 56 [+] Feedback... - Page 46 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.004[0.102] 0°~8° 0.016[0.406] 0.035[0.889] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] Figure 25. 20-Pin (300-Mil) Molded DIP 20-Lead (300-Mil) Molded DIP P5 CY8C24123A CY8C24223A, CY8C24423A MAX. 0.010[0.254] X 45° 0.016[0.406] 0.0075[0.190] 0.0098[0.249] 51-85066 *C 51-85011-A 51-85011 *A Page 46 of 56...
- Page 47 CY8C24123A CY8C24223A, CY8C24423A Figure 26. 20-Pin (210-Mil) SSOP 51-85077 *C Figure 27. 20-Pin (300-Mil) Molded SOIC 51-85024 *C Document Number: 38-12028 Rev. *I Page 47 of 56 [+] Feedback...
- Page 48 CY8C24123A CY8C24223A, CY8C24423A Figure 28. 28-Pin (300-Mil) Molded DIP 51-85014 *D Figure 29. 28-Pin (210-Mil) SSOP 51-85079 *C Document Number: 38-12028 Rev. *I Page 48 of 56 [+] Feedback...
- Page 49 DRAWN STANDARD TOLERANCES ON: DECIMALS ANGLES CHK BY .XXX .XXXX APPROVED BY MATERIAL APPROVED BY CY8C24123A CY8C24223A, CY8C24423A 51-85026 *D 01/29/07 CHANGED SPEC. TITLE, CORRECTED EPAD DIMENSION X = 138 MIL Y = 138 MIL BOTTOM VIEW 3.50 PIN1 ID 0.20 R.
- Page 50 Document Number: 38-12028 Rev. *I CY8C24223A, CY8C24423A Figure 32. 32-Pin Sawn QFN Package Figure 33. 56-Pin (300-Mil) SSOP CY8C24123A S O L D E R A B L E E X P O S E D P A D 001-30999 *A...
- Page 51 28 SOIC 32 QFN Maximum Peak Temperature 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C 260°C CY8C24123A CY8C24223A, CY8C24423A Package Capacitance 2.8 pF 2.0 pF 3.0 pF 2.6 pF 2.5 pF 3.5 pF 2.8 pF 2.7 pF 2.0 pF C with...
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Page 52: Development Kits
MiniEval Socket Programming and Evaluation Board ■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample ■ 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample ■ PSoC Designer Software CD ■ Getting Started Guide ■ USB 2.0 Cable CY8C24123A C buses, voltage Page 52 of 56 [+] Feedback... -
Page 53: Third Party Tools
For details on how to emulate your circuit before going to volume production using an on-chip debug (OCD) non-production PSoC device, see application note under DESIGN Emulator into Your Board”. CY8C24123A CY8C24223A, CY8C24423A Adapter Adapters can be found at http://www.emulation.com. -
Page 54: Ordering Information
The following table lists the CY8C24x23A PSoC device’s key package features and ordering codes. Table 54. CY8C24x23A PSoC Device Key Features and Ordering Information 8 Pin (300 Mil) DIP CY8C24123A-24PXI 8 Pin (150 Mil) SOIC CY8C24123A-24SXI 8 Pin (150 Mil) SOIC... - Page 55 Tool section. Add CY8C20x34 to PSoC Device Characteristics table. Added Sawn pin information. Corrected Ordering Information to include CY8C24423A-24LTXI and CY8C24423A-24LTXIT Changed title to “CY8C24123A, CY8C24223A, CY8C24423A PSoC Programmable System-on-Chip™” Updated package diagram 001-30999 to *A. Added note on digital signaling in...
- Page 56 PSoC Solutions psoc.cypress.com General clocks.cypress.com Low Power/Low Voltage Precision Analog LCD Drive image.cypress.com CAN 2.0b Revised December 11, 2008 CY8C24123A CY8C24223A, CY8C24423A psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb Page 56 of 56 [+] Feedback...
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