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Overview
The Cypress nonvolatile Programmable System-on-Chip
®
(PSoC
NV) processor combines a versatile Programmable
System-on-Chip™ (PSoC) core with an infinite endurance
nvSRAM in a single package. The PSoC NV combines an 8-bit
MCU core (M8C), configurable analog and digital functions, a
uniquely flexible IO interface, and a high density nvSRAM. This
creates versatile data logging solutions that provide value
through component integration and programmability. The flexible
core and a powerful development environment work to reduce
design complexity, component count, and development time.
Features
Powerful Harvard Architecture Processor
■
M8C processor speeds
❐
• Up to 12 MHz for 3.3V operation
• Up to 24 MHz for 5V operation
Two 8x8 multiply, 32 bit accumulate
❐
Low power at high speed
❐
Operating Voltage
■
3.3V (CY8CNP102B)
❐
5V (CY8CNP102E)
❐
Advanced Peripherals
■
12 Rail-to-Rail Analog PSoC blocks provide:
❐
• Up to 14 bit ADCs
• Up to 9 bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
• 8 Analog channels for simultaneous sampling
• Up to 820 SPS for each channel with 8 channel sampling
and logging
16 Digital PSoC Blocks provide:
❐
• 8 to 32 bit timers, counters, and PWMs
• CRC and PRS Modules
• Up to 4 Full Duplex UARTs
• Multiple SPI™ Masters and Slaves
Complex Peripherals by Combining Blocks
❐
Cypress Semiconductor Corporation
Document #: 001-43991 Rev. *D
PRELIMINARY
N
onvolatile Programmable System-on-Chip
Precision, Programmable Clocking
■
Internal ±2.5% 24 and 48 MHz Oscillator
❐
24 and 48 MHz with optional 32.768 kHz Crystal
❐
Optional External Oscillator, up to 24 MHz
❐
Internal Oscillator for Watchdog and Sleep
❐
Flexible On-Chip Memory
■
32K Bytes Flash Program Storage
❐
2K Bytes SRAM Data Storage
❐
256K Bytes secure store nvSRAM with data throughput be-
❐
tween 100 KBPS and 1 MBPS
In-System Serial Programming (ISSP)
❐
Partial Flash Updates
❐
Flexible Protection Modes
❐
EEPROM Emulation in Flash
❐
Programmable Pin Configurations
■
33 GPIOs
❐
25 mA Sink on all GPIO
❐
Pull up, Pull down, High Z, Strong, or Open Drain Drive
❐
Modes on all GPIO
Up to 12 Analog Inputs on GPIOs
❐
Analog Outputs with 40 mA on 4 GPIOs
❐
Configurable Interrupt on all GPIOs
❐
Additional System Resources
■
I
❐
and 400 Kbps
Watchdog and Sleep Timers
❐
Integrated Supervisory Circuit
❐
On-Chip Precision Voltage Reference
❐
Complete Development Tools
■
Free Development Software (PSoC Designer™)
❐
Full Featured, In Circuit Emulator and Programmer
❐
Full Speed Emulation
❐
C Compilers, Assembler, and Linker
❐
Temperature and Packaging
■
Industrial Temperature Range: -40°C to +85°C
❐
Packaging: 100-pin TQFP
❐
•
198 Champion Court
CY8CNP102B, CY8CNP102E
2
C Slave, Master, and MultiMaster to 100 Kbps
,
•
San Jose
CA 95134-1709
PSoC® NV)
(
•
408-943-2600
Revised October 20, 2008
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Related Manuals for Cypress Semiconductor CY8CNP102B
Summary of Contents for Cypress Semiconductor CY8CNP102B
- Page 1 • Up to 24 MHz for 5V operation Two 8x8 multiply, 32 bit accumulate ❐ Low power at high speed ❐ Operating Voltage ■ 3.3V (CY8CNP102B) ❐ 5V (CY8CNP102E) ❐ Advanced Peripherals ■ 12 Rail-to-Rail Analog PSoC blocks provide: ❐...
-
Page 2: Logic Block Diagram
PRELIMINARY CY8CNP102B, CY8CNP102E Logic Block Diagram Document #: 001-43991 Rev. *D Page 2 of 38 [+] Feedback... - Page 3 Reserved for test modes - Do Not Use Reserved for test modes - Do Not Use Not connected on the die GPIO Connect to Pin 26 (EN_W to NV_W) GPIO CY8CNP102B, CY8CNP102E Pin Definition Page 3 of 38 [+] Feedback...
- Page 4 Not connected on the die Analog Column Mux Input, GPIO Power Supply Voltage Connect to Pin 60 (NV_O to EN_O) Reserved for test modes - Do Not Use Not connected on the die CY8CNP102B, CY8CNP102E Pin Definition Page 4 of 38 [+] Feedback...
- Page 5 Vcc to charge a capacitor connected to the V stored charge is used by the chip to perform a STORE operation. If the voltage on the Vcc pin drops below V automatically disconnects the V operation is initiated. CY8CNP102B, CY8CNP102E Pin Definition ® technology ®...
- Page 6 ■ Modulators ■ Correlators ■ Document #: 001-43991 Rev. *D PRELIMINARY CY8CNP102B, CY8CNP102E Peak Detectors ■ Other possible topologies ■ Analog blocks are provided in columns of three, which includes ■ one CT (Continuous Time) and two SC (Switched Capacitor) blocks.
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Page 7: Development Tools
P o d E m u la to r Document #: 001-43991 Rev. *D PRELIMINARY CY8CNP102B, CY8CNP102E PSoC Designer Software Subsystems Device Editor The Device Editor subsystem enables the user to select different onboard analog and digital components called user modules, using the PSoC blocks. - Page 8 Document #: 001-43991 Rev. *D PRELIMINARY CY8CNP102B, CY8CNP102E The development process starts when you open a new project and bring up the Device Editor, which is a graphical user interface (GUI) for configuring the hardware. Pick the user modules required for your project and map them onto the PSoC blocks with point and click simplicity.
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Page 9: Electrical Specifications
C, except where noted. Figure 5. IMO Frequency Trim Options 5.25 4.75 3.60 3.00 12 MHz 24 MHz 93 kHz Symbol μW Ω σ CY8CNP102B, CY8CNP102E SLIMO SLIMO Mode=1 Mode=0 SLIMO SLIMO Mode=1 Mode=0 6 MHz 12 MHz 24 MHz IMO Frequency... -
Page 10: Operation
3.3V Operation Absolute Maximum Ratings Table 3. 3.3V Absolute Maximum Ratings (CY8CNP102B) Symbol Description Storage Temperature Ambient Temperature with Power Applied Supply Voltage on Vcc Relative to Vss DC Input Voltage DC Voltage Applied to Tri-state Maximum Current into any Port Pin... -
Page 11: Dc Electrical Characteristics
The following DC electrical specifications list the guaranteed maximum and minimum specifications for the voltage and temperature range: 3.0V to 3.6V over the Temperature range of -40°C ≤ T guidance only. DC Chip Level Specifications Table 5. 3.3V DC Chip Level Specifications (CY8CNP102B) Symbol Description Supply Voltage... - Page 12 Power = High, Opamp Bias = Low Power = High, Opamp Bias = High PSRR Supply Voltage Rejection Ratio DC Low Power Comparator Specifications Table 8. 3.3V DC Low Power Comparator Specifications (CY8CNP102B) Symbol Description Low power comparator (LPC) reference voltage range REFLPC...
- Page 13 DC Analog Output Buffer Specifications Table 9. 3.3V DC Analog Output Buffer Specifications (CY8CNP102B) Symbol Description Input Offset Voltage (Absolute Value) OSOB Average Input Offset Voltage Drift OSOB Common-Mode Input Voltage Range CMOB Output Resistance OUTOB Power = Low Power = High...
- Page 14 RefLo = P2[4] – BandGap (P2[4] = Vcc/2) – RefLo = P2[4]-P2[6] (P2[4] = Vcc/2, P2[6] = 0.5V) P2[4] - P2[6] - 0.036 DC Analog PSoC NV Block Specifications Table 11. 3.3V DC Analog PSoC NV Block Specifications (CY8CNP102B) Symbol Description Resistor Unit Value (Continuous Time)
- Page 15 DC POR, SMP, and LVD Specifications Table 12. 3.3V DC POR, SMP, and LVD Specifications (CY8CNP102B) Symbol Description Vdd Value for PPOR Trip (positive ramp) PORLEV[1:0] = 00b PPOR0R Vdd Value for PPOR Trip (negative ramp) PORLEV[1:0] = 00b PPOR0...
- Page 16 DC Programming Specifications Table 13. 3.3V DC Programming Specifications (CY8CNP102B) Symbol Description Supply Current During Programming or Verify DDPV Input Low Voltage During Programming or Verify Input High Voltage During Programming or Verify Input Current when Applying Vilp to P1[0] or P1[1]...
-
Page 17: Ac Electrical Characteristics
The following AC electrical specifications list the guaranteed maximum and minimum specifications for the voltage and temperature range: 3.0V to 3.6V over the temperature range of -40°C ≤ T guidance only. AC Chip Level Specifications Table 14. 3.3V AC Chip Level Specifications (CY8CNP102B) Symbol Description Internal Main Oscillator Frequency for... - Page 18 In the following table, t starts from the time Vcc rises above V HRECALL nonvolatile cycle, no STORE occurs. Industrial grade devices require 15 ms maximum. Table 15.3.3V nvSRAM AutoStore/Power Up RECALL (CY8CNP102B) Parameter Description Power Up RECALL Duration HRECALL...
- Page 19 AC Operational Amplifier Specifications Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block. Table 17. 3.3V AC Operational Amplifier Specifications (CY8CNP102B) Symbol Description Rising Settling Time to 0.1% of a 1V Step (10 pF load, Unity Gain)
- Page 20 Table 18. 3.3V AC Digital Block Specifications (CY8CNP102B) (continued) Function Description CRCPRS Maximum Input Clock Frequency (PRS Mode) CRCPRS Maximum Input Clock Frequency (CRC Mode) SPIM Maximum Input Clock Frequency SPIS Maximum Input Clock Frequency Width of SS_ Negated Between Transmissions...
- Page 21 AC Programming Specifications Table 20. 3.3V AC Programming Specifications (CY8CNP102B) Symbol Description Rise Time of SCLK RSCLK Fall Time of SCLK FSCLK Data Set up Time to Falling Edge of SCLK SSCLK Data Hold Time from Falling Edge of SCLK...
- Page 22 Voltage Latch-up Current Operating Temperature Table 23. 5V Operating Temperature (CY8CNP102E) Symbol Description Ambient Temperature Junction Temperature Document #: 001-43991 Rev. *D PRELIMINARY CY8CNP102B, CY8CNP102E +100 – -0.5 – +6.0 Vss - 0.5 – Vcc + 0.5 Vss - 0.5 –...
- Page 23 Input Leakage (Absolute Value) Capacitive Load on Pins as Input Capacitive Load on Pins as Output Document #: 001-43991 Rev. *D PRELIMINARY CY8CNP102B, CY8CNP102E ≤ 85°C. Typical parameters apply to 5V at 25°C and are for design Units 4.75 –...
- Page 24 Table 27. 5V DC Low Power Comparator Specifications (CY8CNP102E) Symbol Description Low power comparator (LPC) reference voltage range REFLPC LPC supply current SLPC LPC voltage offset OSLPC Document #: 001-43991 Rev. *D PRELIMINARY CY8CNP102B, CY8CNP102E Units – – – μV/ – 35.0 – – –...
- Page 25 P2[4] + P2[6] - 0.058 P2[4] + P2[6] P2[4] + P2[6] + 0.058 2.50 4.02 /2 - 1.369 1.20 2.489 - P2[6] P2[4] - 1.368 P2[4] - P2[6] - 0.042 P2[4] - P2[6] P2[4] - P2[6] + 0.042 CY8CNP102B, CY8CNP102E – – Vcc - 1.0 – – – –...
- Page 26 VM[2:0] = 011b PUMP3 VM[2:0] = 100b PUMP4 VM[2:0] = 101b PUMP5 VM[2:0] = 110b PUMP6 VM[2:0] = 111b PUMP7 Document #: 001-43991 Rev. *D PRELIMINARY CY8CNP102B, CY8CNP102E – 12.2 – 2.91 4.39 4.55 2.82 4.39 4.55 2.86 2.92 2.96 3.02...
- Page 27 Output High Voltage During Programming or Verify Flash Flash Endurance (per block) ENPB Flash Flash Endurance (total) Flash Flash Data Retention Document #: 001-43991 Rev. *D PRELIMINARY CY8CNP102B, CY8CNP102E – – – – – – – – – – –...
- Page 28 Maximum frequency of signal on row input or row output. Supply Ramp Time RAMP Document #: 001-43991 Rev. *D PRELIMINARY CY8CNP102B, CY8CNP102E ≤ 85°C. Typical parameters apply to 5V at 25°C and are for design [4, 5, 6] 23.4 24.6 [4 , 5, 6] 5.75...
- Page 29 If an SRAM WRITE has not taken place since the last SWITCH. Description – – – Figure 7. GPIO Timing Diagram TRiseF TFallF TRiseS TFallS CY8CNP102B, CY8CNP102E nvSRAM Unit 12.5 μs Units Notes 12.3 MHz Normal Strong Mode Vcc = 4.75V to 5.25V 10% - 90% Vcc = 4.75V to 5.25V...
- Page 30 Dead Band Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency CRCPRS Maximum Input Clock Frequency (PRS Mode) Document #: 001-43991 Rev. *D PRELIMINARY CY8CNP102B, CY8CNP102E Description – – – – – – – – –...
- Page 31 Power = High Small Signal Bandwidth, 20mV Power = Low Power = High Large Signal Bandwidth, 1V Power = Low Power = High Document #: 001-43991 Rev. *D PRELIMINARY CY8CNP102B, CY8CNP102E – – – – – – – – –...
- Page 32 Pulse Width of spikes are suppressed by the input filter. SPI2C Document #: 001-43991 Rev. *D PRELIMINARY – – – C SDA and SCL Pins (CY8CNP102E) Standard Mode – CY8CNP102B, CY8CNP102E Units Notes – – – – – – –...
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Page 33: Switching Waveforms
STORE HRECALL Figure 9. PLL Lock Timing Diagram P L L S L E W P L L S L E W L O W CY8CNP102B, CY8CNP102E STORE occurs only No STORE occurs if a SRAM write without atleast one... - Page 34 Document #: 001-43991 Rev. *D PRELIMINARY J it t e r 2 4 M 1 SUDATI2C HDSTAI2C SUSTAI2C HIGHI2C CY8CNP102B, CY8CNP102E 3 2 k H z J it t e r 3 2 k C Bus BUFI2C SPI2C SUSTOI2C Page 34 of 38...
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Page 35: Part Numbering Nomenclature
E = 5V Density: 01 = 1Mb 02 = 2Mb 12 = 512Kb Package Diagram 51 - 85048 51 - 85048 CY8CNP102B, CY8CNP102E Temp: C = Commercial I = Industrial X = Pb free A = 100TQFP Package Type Operating Range... -
Page 36: Packaging Information
PRELIMINARY CY8CNP102B, CY8CNP102E Packaging Information This section describes the packaging specifications for the PSoC NV device and the thermal impedances for TQFP package. Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of the emulation tool dimensions, refer to the document “PSoC Emulator Pod Dimensions”... - Page 37 Document History Page Document Title: CY8CNP102B/CY8CNP102E Nonvolatile Programmable System-on-Chip (PSoC® NV) Document Number: 001-43991 Submission REV. Orig. of Change 1941108 vsutmp8/AESA 2378513 PYRS 2512803 GVCH/PYRS 06/05/2008 2571208 GVCH/PYRS 2594976 GVCH/PYRS Document #: 001-43991 Rev. *D PRELIMINARY Description of Change Date...
- Page 38 PRELIMINARY PSoC Solutions General psoc.cypress.com Low Power/Low Voltage clocks.cypress.com Precision Analog LCD Drive CAN 2.0b image.cypress.com Revised October 20, 2008 CY8CNP102B, CY8CNP102E psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb Page 38 of 38 [+] Feedback...
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