Cypress CY14B108K Specification Sheet page 23

Hardware STORE Cycle
Parameters
t HSB To Output Active Time when write latch not set
DHSB
t Hardware STORE Pulse Width
PHSB
Switching Waveforms
Write latch set
HSB (IN)
HSB (OUT)
DQ (Data Out)
RWI
Write latch not set
HSB (IN)
HSB (OUT)
RWI
Address Address #1
CE
V
CC
Notes
31. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
32. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.
Document #: 001-47378 Rev. **
PRELIMINARY
Description
Figure 15. Hardware STORE Cycle
t
PHSB
t
DELAY
t
PHSB
t
t
DELAY
DHSB
Figure 16. Soft Sequence Processing
t
Soft Sequence
Command
Address #6
t t
SA CW
20 ns
Min Max
20
15
[23]
t
STORE
HSB pin is driven high to V
100kOhm resistor,
HSB driver is disabled
SRAM is disabled as long as HSB (IN) is driven low.
t
DHSB
[31, 32]
Soft Sequence
SS
Command
Address #1 Address #6
CY14B108K, CY14B108M
25 ns 45 ns
Min Max Min
25
15 15
t
HHHD
t
LZHSB
only by Internal
CC
t
SS
t
CW
Page 23 of 29
Unit
Max
25 ns
ns
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