Cypress CY14B108K Specification Sheet page 19

Switching Waveforms
Address
CE
OE
BHE, BLE
High Impedance
Data Output
I
CC
Address
CE
BHE, BLE
WE
Data Input
Data Output
Note
20. CE or WE must be >V during address transitions.
IH
Document #: 001-47378 Rev. **
PRELIMINARY
Figure 8. SRAM Read Cycle 2: CE Controlled
Address Valid
t
ACE
t
AA
t
LZCE
t
LZOE
t
LZBE
t
PU
Standby
Figure 9. SRAM Write Cycle 1: WE Controlled
t
AW
t
SA
Previous Data
CY14B108K, CY14B108M
[3, 15, 19]
t
RC
t
DOE
t
DBE
Output Data Valid
Active
[3, 18, 19, 20]
t
WC
Address Valid
t t
SCE HA
t
BW
t
PWE
t
t
HD
SD
Input Data Valid
t
t
LZWE
HZWE
High Impedance
t
HZCE
t
HZOE
t
HZBE
t
PD
Page 19 of 29
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