Cypress CY14B108K Specification Sheet page 20

Switching Waveforms
Address
CE
BHE, BLE
WE
Data Input
Data Output
Figure 11. SRAM Write Cycle 3: BHE and BLE Controlled
Address
CE
BHE, BLE
WE
Data Input
Data Output
Note
21. Only CE and WE controlled writes to RTC registers are allowed. BLE pin must be held LOW before CE or WE pin goes LOW for writes to RTC register.
Document #: 001-47378 Rev. **
PRELIMINARY
Figure 10. SRAM Write Cycle 2: CE Controlled
Address Valid
t t
SA SCE
t
BW
t
PWE
High Impedance
(Not applicable for RTC register writes)
Address Valid
t
SCE
t
t
SA
BW
t
AW
t
PWE
High Impedance
CY14B108K, CY14B108M
[3, 18, 19, 20]
t
WC
t
HA
t t
SD HD
Input Data Valid
[5, 18, 19, 20, 21]
t
WC
t
HA
t t
SD HD
Input Data Valid
Page 20 of 29
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