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Cypress Semiconductor Quad HOTLink II CYV15G0404RB Specification Sheet

Independent clock deserializing reclocker
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Features
• Second-generation HOTLink
• Compliant to SMPTE 292M and SMPTE 259M video
standards
• Quad channel video reclocking deserializer
— 195 to 1500 Mbps serial data signaling rate
— Simultaneous operation at different signaling rates
• Supports reception of either 1.485 or 1.485/1.001 Gbps data
rate with the same training clock
• Supports half-rate and full-rate clocking
• Internal phase-locked loops (PLLs) with no external PLL
components
• Selectable differential PECL-compatible serial inputs
— Internal DC restoration
• Synchronous LVTTL parallel interface
• JTAG boundary scan
• Built-In Self-Test (BIST) for at-speed link testing
• Link Quality Indicator
— Analog signal detect
— Digital signal detect
• Low-power: 3W @ 3.3V typical
• Single 3.3V supply
• Thermally enhanced BGA
• Pb-Free package option available
• 0.25µ BiCMOS technology
Functional Description
The CYV15G0404RB Independent Clock Quad HOTLink II™
Deserializing Reclocker is a point-to-point or point-to-multi-
point communications building block enabling data transfer
over a variety of high speed serial links including SMPTE 292
Cypress Semiconductor Corporation
Document #: 38-02102 Rev. *C
Independent Clock Quad HOTLink II™
®
technology
•
198 Champion Court
Deserializing Reclocker
and SMPTE 259 video applications. It supports signaling rates
in the range of 195 to 1500 Mbps for each serial link. The four
channels are independent and can simultaneously operate at
different rates. Each receive channel accepts serial data and
converts it to 10-bit parallel characters and presents these
characters to an Output Register. The received serial data can
also be reclocked and retransmitted through the reclocker
serial outputs.
Figure 1, "HOTLink II™ System Connections,"
on page 2
illustrates typical connections between independent
video coprocessors and corresponding CYV15G0404RB
Reclocking Deserializer and CYV15G0403TB Serializer chips.
The CYV15G0404RB is SMPTE-259M and SMPTE-292M
compliant according to SMPTE EG34-1999 Pathological Test
Requirements.
As
a
second
generation
CYV15G0404RB extends the HOTLink family with enhanced
levels of integration and faster data rates, while maintaining
serial-link compatibility (data and BIST) with other HOTLink
devices.
Each channel of the CYV15G0404RB Quad HOTLink II device
accepts a serial bit-stream from one of two selectable
PECL-compatible differential line receivers, and using a
completely integrated Clock and Data Recovery PLL, recovers
the timing information necessary for data reconstruction. The
device reclocks and retransmits recovered bit-stream through
the reclocker serial outputs. It also deserializes the recovered
serial data and presents it to the destination host system.
Each channel contains an independent BIST pattern checker.
This BIST hardware enables at speed testing of the
high-speed serial data paths in each receive section of this
device, each transmit section of a connected HOTLink II
device, and across the interconnecting links.
The CYV15G0404RB is ideal for SMPTE applications where
different data rates and serial interface standards are
necessary for each channel. Some applications include
multi-format routers, switchers, format converters, SDI
monitors, and camera control units.
,
•
San Jose
CA 95134-1709
CYV15G0404RB
HOTLink
device,
the
•
408-943-2600
Revised February 16, 2007
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Summary of Contents for Cypress Semiconductor Quad HOTLink II CYV15G0404RB

  • Page 1 Each channel of the CYV15G0404RB Quad HOTLink II device accepts a serial bit-stream from one of two selectable PECL-compatible differential line receivers, and using a completely integrated Clock and Data Recovery PLL, recovers the timing information necessary for data reconstruction. The device reclocks and retransmits recovered bit-stream through the reclocker serial outputs.
  • Page 2 Independent Channel CYV15G0403TB Serializer CYV15G0404RB Deserializing Reclocker Logic Block Diagram Deserializer Reclocker Reclocker Document #: 38-02102 Rev. *C Figure 1. HOTLink II™ System Connections Reclocked Outputs CYV15G0404RB Serial Links Reclocking Deserializer Reclocked Outputs Deserializer Deserializer Reclocker CYV15G0404RB Independent Channel Deserializer Reclocker Page 2 of 27 [+] Feedback...
  • Page 3 TRGCLKA SDASEL[2..1]A[1:0] LDTDEN Receive Signal INSELA Monitor INA1+ INA1– Clock & INA2+ Data INA2– Recovery ULCA SPDSELA RXPLLPDA Recovered Character Clock RECLKOA Character-Rate Clock A REPDOA TRGRATEB TRGCLKB SDASEL[2..1]B[1:0] LDTDEN Receive Signal INSELB Monitor INB1+ INB1– Clock & INB2+ Data INB2–...
  • Page 4 TRGCLKC SDASEL[2..1]C[1:0] LDTDEN Receive Signal INSELC Monitor INC1+ INC1– Clock & INC2+ Data Recovery INC2– ULCC SPDSELC RXPLLPDC Recovered Character Clock RECLKOC Character-Rate Clock C REPDOC TRGRATED TRGCLKD SDASEL[2..1]D[1:0] LDTDEN Receive Signal INSELD Monitor IND1+ IND1– Clock & IND2+ Data IND2–...
  • Page 5 Device Configuration and Control Block Diagram WREN Device Configuration ADDR[3:0] and Control Interface DATA[7:0] Document #: 38-02102 Rev. *C CYV15G0404RB RXBIST[A..D] RXRATE[A..D] SDASEL[A..D][1:0] RXPLLPD[A..D] ROE[2..1][A..D] GLEN[11..0] FGLEN[2..0] = Internal Signal Page 5 of 27 [+] Feedback...

  • Page 6: Pin Configuration (Top View)

    Pin Configuration (Top View) ROUT ROUT C1– C1– C2– C2– D1– ROUT ROUT INSELC INSELB ULCD TCLK RESET INSELD INSELA ULCA DC[8] DC[9] WREN DC[4] CLKC– LFIC DC[5] CLKC+ DC[6] DC[7] PDOC DC[3] DC[2] DC[1] DC[0] BIST CLKOC CLKC+ CLKC– DD[4] DD[8] DD[5]...
  • Page 7 Pin Configuration (Bottom View) ROUT ROUT ROUT B2– B2– B1– B1– A2– ROUT ROUT ROUT TRST LDTD SELD TMEN3 SCAN ULCB DB[1] CLKOB DB[0] DB[3] SELA SELB BIST DB[4] DB[7] DB[2] LFIB DB[9] DB[6] DB[5] CLKB– CLKB+ DB[8] PDOB CLKB– CLKB+ BIST DA[0]...
  • Page 8 PLL uses the TRGCLKx± clock inputs as the reference source to reduce PLL acquisition time. In the presence of valid serial data, the recovered clock output of the receive CDR PLL (RXCLKx±) has no frequency or phase relationship with TRGCLKx±.
  • Page 9 Range Controller determines if the RXPLL tracks TRGCLKx± or the selected input serial data stream. Set LDTDEN = HIGH. Use Local Clock. When ULCx is LOW, the RXPLL locks to TRGCLKx± instead of the received serial data stream. While ULCx is LOW, the LFIx for the associated channel is LOW, indicating a link fault.
  • Page 10 RESET is asserted. Table 4, “Device Control Latch Configuration Table,” on page 16 the way the latches are mapped in the device. Receive Clock Rate Select. Signal Detect Amplitude Select. Receive Channel Power Control. Receive BIST Disabled.
  • Page 11 AC coupled signals. Signal Detect/Link Fault Each selected Line Receiver (that is, that routed to the clock and data recovery PLL) is simultaneously monitored for • Analog amplitude above amplitude level selected by SDASELx •...
  • Page 12 Clock/Data Recovery A separate CDR block within each receive channel performs the extraction of a bit rate clock and recovery of bits from each received serial stream. An integrated PLL that tracks the frequency of the transitions in the incoming bit stream and aligns the phase of the internal bit rate clock to the transitions Document #: 38-02102 Rev.

  • Page 13: Power Control

    reclocker serial drivers for a channel are in this disabled state, the associated internal reclocker logic also powers down. The deserialization logic and parallel outputs remain enabled. A device reset (RESET sampled LOW) disables all output drivers. Note When the disabled reclocker function (that is, both outputs disabled) is reenabled, the data on the reclocker serial outputs may not meet all timing specifications for up to 250 µs.
  • Page 14 Table 3. Device Configuration and Control Latch Descriptions Name Signal Description RXRATEA Receive Clock Rate Select. The initialization value of the RXRATEx latch = 1. RXRATEx selects the rate RXRATEB of the RXCLKx± clock output. RXRATEC When RXRATEx = 1, the RXCLKx± clock outputs are complementary clocks that follow the recovered RXRATED clock operating at half the character rate.
  • Page 15 Table 3. Device Configuration and Control Latch Descriptions (continued) Name Signal Description RXPLLPDA Receive Channel Enable. The initialization value of the RXPLLPDx latch = 0. RXPLLPDx selects whether RXPLLPDB the associated receive channel is enabled or powered down. RXPLLPDx = 0 powers down the associated RXPLLPDC receive PLL and analog circuitry.
  • Page 16 Table 4. Device Control Latch Configuration Table ADDR Channel Type DATA7 DATA6 (0000b) SDASEL2A[1] SDASEL2A[0] (0001b) RXBISTA[1] RXPLLPDA (0010b) (0011b) SDASEL2B[1] SDASEL2B[0] (0100b) RXBISTB[1] RXPLLPDB (0101b) (0110b) SDASEL2C[1] SDASEL2C[0] (0111b) RXBISTC[1] RXPLLPDC (1000b) (1001b) SDASEL2D[1] SDASEL2D[0] (1010b) RXBISTD[1] RXPLLPDD (1011b) GLOBAL (1100b) GLOBAL...

  • Page 17: Jtag Support

    This capability is present only on the LVTTL inputs and outputs and the TRGCLKx± clock input. The high-speed serial inputs and outputs are not part of the JTAG test chain. To ensure valid device operation after power-up (including non-JTAG operation), the JTAG state machine must also be initialized to a reset state.
  • Page 18 CYV15G0404RB Figure 2. Receive BIST State Machine Monitor Data Receive BIST Received Detected LOW {BISTSTx, RXDx[0], RX PLL RXDx[1]} = Out of Lock BIST_START (101) {BISTSTx, RXDx[0], RXDx[1]} = BIST_WAIT (111) Start of BIST Detected Yes, {BISTSTx, RXDx[0], RXDx[1]} = BIST_DATA_COMPARE (000, 001) Compare Next Character...

  • Page 19: Maximum Ratings

    Maximum Ratings Excedding maximum ratings may shorten the device life. User guidelines are not tested Storage Temperature ... –65°C to +150°C Ambient Temperature with Power Applied... –55°C to +125°C Supply Voltage to Ground Potential ... –0.5V to +3.8V DC Voltage Applied to LVTTL Outputs in High-Z State ...–0.5V to V Output Current into LVTTL Outputs (LOW)...60 mA DC Input Voltage...–0.5V to V...
  • Page 20 CYV15G0404RB DC Electrical Characteristics Parameter Description Differential CML Serial Outputs: ROUTA1±, ROUTA2±, ROUTB1±, ROUTB2±, ROUTC1±, ROUTC2±, ROUTD1±, ROUTD2± Output HIGH Voltage Referenced) Output LOW Voltage Referenced) Output Differential Voltage ODIF |(OUT+) − (OUT−)| Differential Serial Line Receiver Inputs: INA1±, INA2±, INB1±, INB2±, INC1±, INC2±, IND1±, IND2± Input Differential Voltage |(IN+) −...
  • Page 21 15. The ratio of rise time to falling time must not vary by greater than 2:1. 16. For a given operating frequency, neither rise nor fall specification can be greater than 20% of the clock cycle period or the data sheet maximum time.

  • Page 22: Pll Characteristics

    CYV15G0404RB AC Electrical Characteristics Parameter CYV15G0404RB Device RESET Characteristics Over the Operating Range Device RESET Pulse Width CYV15G0404RB Reclocker Serial Output Characteristics Over the Operating Range Parameter Description Bit Time [14] CML Output Rise Time 20−80% (CML Test Load) RISE [14] CML Output Fall Time 80−20% (CML Test Load) FALL...
  • Page 23 Switching Waveforms for the CYV15G0404RB HOTLink II Receiver Receive Interface Read Timing RXRATEx = 0 RXCLKx+ RXCLKx– RXDx[9:0] Receive Interface Read Timing RXRATEx = 1 RXCLKx+ RXCLKx– RXDx[9:0] CYV15G0404RB HOTLink II Bus Configuration Switching Waveforms Bus Configuration Write Timing ADDR[3:0] DATA[7:0] WREN Document #: 38-02102 Rev.
  • Page 24 Table 6. Package Coordinate Signal Allocation Ball Signal Name Signal Type INC1– CML IN ROUTC1– CML OUT INC2– CML IN ROUTC2– CML OUT POWER IND1– CML IN ROUTD1– CML OUT GROUND IND2– CML IN ROUTD2– CML OUT INA1– CML IN ROUTA1–...
  • Page 25 Table 6. Package Coordinate Signal Allocation (continued) Ball Signal Name Signal Type ROUTB2+ CML OUT LVTTL IN PU LVTTL IN PU INSELC LVTTL IN INSELB LVTTL IN POWER ULCD LVTTL IN PU POWER REPDOC LVTTL OUT TRGCLKB+ PECL IN TRGCLKB– PECL IN REPDOB LVTTL OUT...
  • Page 26 Table 6. Package Coordinate Signal Allocation (continued) Ball Signal Name Signal Type POWER POWER POWER POWER POWER POWER POWER POWER Ordering Information Speed Ordering Code Standard CYV15G0404RB-BGC Standard CYV15G0404RB-BGXC Package Diagram Figure 3. 256-Lead L2 Ball Grid Array (27 x 27 x 1.57 mm) BL256 TOP VIEW 27.00±0.13 A1 CORNER I.D.
  • Page 27 Document History Page Document Title: CYV15G0404RB Independent Clock Quad HOTLink II™ Deserializing Reclocker Document Number: 38-02102 ISSUE REV. ECN NO. DATE 246850 See ECN 338721 See ECN 384307 See ECN 789283 See ECN Document #: 38-02102 Rev. *C ORIG. OF...