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Features
• True dual-ported memory cells which allow simulta-
neous access of the same memory location
• 4/8/16k × 16 and 8/16k × 8 organization
• High-speed access: 40 ns
• Ultra Low operating power
— Active: I
= 15 mA (typical) at 55 ns
CC
— Active: I
= 25 mA (typical) at 40 ns
CC
= 2 µA (typical)
— Standby: I
SB3
• Port-independent 1.8V, 2.5V, and 3.0V I/Os
Selection Guide for V
CC
Port I/O Voltages (P1-P2)
Maximum Access Time
Typical Operating Current
Typical Standby Current for I
Typical Standby Current for I
Selection Guide for V
CC
Port I/O Voltages (P1-P2)
Maximum Access Time
Typical Operating Current
Typical Standby Current for I
Typical Standby Current for I
Selection Guide for V
CC
Port I/O Voltages (P1-P2)
Maximum Access Time
Typical Operating Current
Typical Standby Current for I
Typical Standby Current for I
Cypress Semiconductor Corporation
Document #: 001-01638 Rev. *E
1.8V 4k/8k/16k x 16 and 8k/16k x 8
= 1.8V
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
-40
1.8V-1.8V
40
25
2
SB1
2
SB3
= 2.5V
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
-40
2.5V-2.5V
40
39
6
SB1
4
SB3
= 3.0V
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
-40
3.0V-3.0V
40
49
7
SB1
6
SB3
•
198 Champion Court
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
ConsuMoBL Dual-Port Static RAM
• Lead (Pb)-free 14 x 14 x 1.4 mm 100-pin TQFP Package
• Full asynchronous operation
• Pin select for Master or Slave
• Expandable data bus to 32 bits with Master/Slave chip
select when using more than one device
• On-chip arbitration logic
• On-chip semaphore logic
• Input Read Registers and Output Drive Registers
• INT flag for port-to-port communication
• Separate upper-byte and lower-byte control
• Commercial and industrial temperature ranges
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
,
•
San Jose
CA 95134-1709
CYDC064B08
-55
1.8V-1.8V
55
15
2
2
-55
2.5V-2.5V
55
28
6
4
CYDC064B08
-55
3.0V-3.0V
55
42
7
6
•
408-943-2600
Revised January 25, 2007
Unit
ns
mA
µA
µA
Unit
ns
mA
µA
µA
Unit
ns
mA
µA
µA
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Related Manuals for Cypress Semiconductor CYDC064B08
Summary of Contents for Cypress Semiconductor CYDC064B08
- Page 1 • Input Read Registers and Output Drive Registers • INT flag for port-to-port communication • Separate upper-byte and lower-byte control • Commercial and industrial temperature ranges CYDC256B16, CYDC128B16, CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B16, CYDC128B08, CYDC064B08 1.8V-1.8V CYDC256B16, CYDC128B16, CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B16, CYDC128B08, CYDC064B08 2.5V-2.5V...
- Page 2 Address Decode Address Decode Interrupt Arbitration Semaphore Input Read Register and Output Drive Register SFEN [1, 2] Figure 1. Top Level Block Diagram –A for 16k devices. CYDC064B08 I/O[15:0] A [13:0] BUSY - ODR Page 2 of 26 [+] Feedback...
-
Page 3: Pin Configurations
CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, 100-Pin TQFP (Top View) 92 91 90 87 86 83 82 81 CYDC064B16 CYDC128B16 CYDC256B16 34 35 36 39 40 43 44 45 CYDC064B08 78 77 BUSY IRR1 DDIOR 48 49 Page 3 of 26 [+] Feedback... - Page 4 10. This pin is A13R for CYDC128B08 devices. Document #: 001-01638 Rev. *E CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, 100-pin TQFP (Top View) 92 91 90 87 86 83 82 81 CYDC064B08 CYDC128B08 34 35 36 39 40 43 44 45 CYDC064B08 78 77 BUSY...
-
Page 5: Functional Description
Lower Byte Select (I/O Interrupt Flag BUSY BUSY Busy Flag IRR0, IRR1 Input Read Register for CYDC064B16, CYDC064B08, CYDC128B16. A13L, A13R for CYDC256B16 and CYDC128B08 devices. ODR0-ODR4 Output Drive Register; These outputs are Open Drain. SFEN Special Function Enable Master or Slave Select... - Page 6 The upper two memory locations may be used for message passing. The highest memory location (FFF for the CYDC064B16, 1FFF for the CYDC128B16 and CYDC064B08, 3FFF for the CYDC256B16 and CYDC128B08) is the mailbox for the right port and the second-highest memory location (FFE...
- Page 7 “1” to all eight semaphores. Architecture CYDC256B16, CYDC128B16, CYDC128B08, CYDC064B08 consist of an array of 4k, 8k, or 16k words of 16 dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). The CYDC064B08 and Table 1. Non-Contending Read/Write Inputs Table 2.
- Page 8 Left port obtains semaphore token Semaphore-free Right port has semaphore token Semaphore free Left port has semaphore token Semaphore-free then DQ<15:8> are valid. . It is inactive when CE = CE CYDC064B08 –I/O Mode [17] [17] VALID Standard Memory Access [18] IRR Read –I/O...
-
Page 9: Maximum Ratings
Range Commercial + 0.5V Industrial + 0.5V = 1.8V Over the Operating Range CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 P1 I/O P2 I/O Voltage Voltage Min. 1.8V (any port) DDIO – 0.2 2.5V (any port) 3.0V (any port) 1.8V (any port) 2.5V (any port) - Page 10 (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby I Document #: 001-01638 Rev. *E CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, = 1.8V (continued) Over the Operating Range CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 P1 I/O P2 I/O Voltage Voltage Min. 1.8V 1.8V –1 2.5V 2.5V –1...
- Page 11 , f = f Document #: 001-01638 Rev. *E CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, = 2.5V Over the Operating Range CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 P1 I/O P2 I/O Voltage Voltage Min. 2.5V (any port) 3.0V (any port) 2.5V (any port) 3.0V (any port) = 8 mA) 2.5V (any port)
- Page 12 26. Tested initially and after any design or process changes that may affect these parameters. Document #: 001-01638 Rev. *E CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, Over the Operating Range CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 P1 I/O P2 I/O Voltage Voltage Min. 3.0V (any port) 3.0V (any port) = 8 mA) 3.0V (any port)
- Page 13 ALL INPUT PULSES ≤ 3 ns ≤ 3 ns = 1.8V [27] Over the Operating Range CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Min. Max. /2, input pulse levels of 0 to V is less than t and t HZCE LZCE HZOE CYDC064B08 3.0V/2.5V/1.8V...
- Page 14 Document #: 001-01638 Rev. *E CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, [27] = 1.8V Over the Operating Range CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Min. Max. –t (actual) or t –t (actual). CYDC064B08 (continued) CYDC256B16, CYDC128B16,...
- Page 15 R/W HIGH after BUSY HIGH (Slave) [35] BUSY HIGH to Data Valid Document #: 001-01638 Rev. *E CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, = 2.5V Over the Operating Range CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Min. Max. CYDC064B08 CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Min. Max. Unit...
- Page 16 Data Hold From Write End Document #: 001-01638 Rev. *E CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, = 2.5V Over the Operating Range (continued) CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Min. Max. = 3.0V Over the Operating Range CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Min.
- Page 17 SEM Flag Contention Window SEM Address Access Time Document #: 001-01638 Rev. *E CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, = 3.0V Over the Operating Range (continued) CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Min. Max. CYDC064B08 CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 Unit Min. Max.
-
Page 18: Switching Waveforms
[36, 39, 40] LZOE LZCE LZCE LZCE . This waveform cannot be used for semaphore reads. . To access semaphore, CE = V , SEM = V CYDC064B08 HZCE HZOE DATA VALID HZCE HZCE Page 18 of 26 [+] Feedback... - Page 19 [41, 42, 43, 44, 45, 46] [44] [47] HZWE [41, 42, 43, 48] or (t HZWE CYDC064B08 [47] HZOE LZWE NOTE 48 ) to allow the I/O drivers to turn off and data to Page 19 of 26 [+] Feedback...
- Page 20 Document #: 001-01638 Rev. *E CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, [49, 50] VALID ADRESS DATA VALID SWRD WRITE CYCLE READ CYCLE [51, 52] MATCH MATCH = CE = HIGH. CYDC064B08 DATA VALID Page 20 of 26 [+] Feedback...
- Page 21 BUSY DATA OUTL Write Timing with Busy Input (M/S = LOW) BUSY Note: 53. CE = CE = LOW. Document #: 001-01638 Rev. *E CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, [53] MATCH VALID MATCH CYDC064B08 VALID Page 21 of 26 [+] Feedback...
- Page 22 BUSY will be asserted. Document #: 001-01638 Rev. *E CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, ADDRESS MATCH ADDRESS MATCH [54] or t ADDRESS MISMATCH or t ADDRESS MISMATCH CYDC064B08 Page 22 of 26 [+] Feedback...
- Page 23 (CE or R/W Document #: 001-01638 Rev. *E CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, [55] READ 1FFF (OR 1/3FFF) [56] [55] READ 1FFE OR 1/3FFE) [56] ) is asserted last. CYDC064B08 Page 23 of 26 [+] Feedback...
-
Page 24: Ordering Information
16k x8 1.8V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code CYDC128B08-40AXC CYDC128B08-55AXC CYDC128B08-55AXI 8k x8 1.8V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code CYDC064B08-40AXC CYDC064B08-55AXC CYDC064B08-55AXI Document #: 001-01638 Rev. *E CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, Package Name Package Type AZ0AB 100-pin Lead-free TQFP... -
Page 25: Package Diagram
The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08 51-85048-*C Page 25 of 26 [+] Feedback... - Page 26 Document History Page Document Title: CYDC256B16/CYDC128B16/CYDC064B16/CYDC128B08/CYDC064B08 1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM Document Number: 001-01638 REV. ECN NO. Issue Date 385185 SEE ECN 396697 SEE ECN 404777 SEE ECN 463014 SEE ECN 505803 SEE ECN...
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