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Tews Technologies TXMC639 User Manual

Reconfigurable fpga with 16 x 16 bit analog input, 8 x 16 bit analog output and 32 digital i/o
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The Embedded I/O Company
TXMC639
Reconfigurable FPGA with 16 x 16 bit Analog Input,
8 x 16 bit Analog Output and 32 digital I/O
Version 1.0
User Manual
Issue 1.0.2
January 2024
TEWS TECHNOLOGIES GmbH
Am Bahnhof 7
25469 Halstenbek, Germany
Phone: +49 (0) 4101 4058 0
Fax: +49 (0) 4101 4058 19
e-mail:
info@tews.com
www.tews.com

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Summary of Contents for Tews Technologies TXMC639

  • Page 1 8 x 16 bit Analog Output and 32 digital I/O Version 1.0 User Manual Issue 1.0.2 January 2024 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek, Germany Phone: +49 (0) 4101 4058 0 Fax: +49 (0) 4101 4058 19 e-mail: info@tews.com...
  • Page 2 16 x Analog In, 8 x Analog Out, 32 TTL (with 16 differential-selectable) Front I/O and 64 direct rear TEWS TECHNOLOGIES GmbH is not liable for any FPGA I/O Lines, damage arising out of the application or use of the device described herein.
  • Page 3 May 2023 Reduction of the ADC digital output coding values to 2 decimal 1.0.1 September 2023 places for better adaptation to the 16 bit correction values. 1.0.2 General Revision January 2024 TXMC639 User Manual Issue 1.0.2 Page 3 of 95...

  • Page 4: Table Of Contents

    Reference DAC Voltage Control Register – 0x10 to 0x4C ............. 21 5.2.5 Digital I/O Interface Configuration /Status Register - 0x60 ............. 23 5.2.6 TXMC639 I/O Area Temperature Sensor Register - 0x64............25 5.2.1 User FPGA JTAG Control and Status Register – 0x80 ............26 5.2.2 User FPGA JTAG Signal Line Register –...
  • Page 5 JTAG Controller to User FPGA JTAG Interface ................. 83 7.15.1 bit-IO ............................83 7.15.2 Vector-IO ..........................83 I2C Bridge ............................84 On-Board Indicators ........................85 7.17.1 User FPGA LED Pinning ......................86 User FPGA Reset Inputs ......................86 TXMC639 User Manual Issue 1.0.2 Page 5 of 95...
  • Page 6 FIGURE 10-1 : FRONT PANEL I/O CONNECTOR NUMBERING ..............91 FIGURE 10-2 : PIN ASSIGNMENT P14 REAR I/O CONNECTOR ..............93 FIGURE 10-3 : PIN ASSIGNMENT P16 REAR I/O CONNECTOR ..............94 TXMC639 User Manual Issue 1.0.2 Page 6 of 95...
  • Page 7 TABLE 5-5 : VOLTAGE CODING FOR THE REFERENCE DAC..............22 TABLE 5-6 : I/O PULL-RESISTOR CONFIGURATION REGISTER..............24 TABLE 5-7 : TXMC639 I/O AREA TEMPERATURE SENSOR REGISTER ............ 25 TABLE 5-8 : USER FPGA JTAG CONTROL AND STATUS REGISTER ............26 TABLE 5-9 : USER FPGA JTAG SIGNAL LINE REGISTER ................
  • Page 8 TABLE 7-22 : XMC P16 DIGITAL I/O INTERFACE ..................82 TABLE 7-23: BOARD-STATUS AND USER LEDS..................85 TABLE 7-24: TXMC639 USER ON-BOARD INDICATORS ................86 TABLE 7-25: USER FPGA RESET INPUTS ....................86 TABLE 9-1 : DIFFERENTIAL INPUT VOLTAGE .................... 88 TABLE 9-2 : DAC ELECTRICAL INTERFACE....................

  • Page 9: Product Description

    ±20.56 V, ±10.28 V or ±5.14 V. The TXMC639 DAC output channels are based on the Dual 16bit AD5547 DAC. Each DAC output is designed as a configurable single-ended bipolar analog output. Output voltage is configurable as Single Ended ±10.0 V, ±5.0 V or ±2.5 V.

  • Page 10: Technical Specification

    PCI Express to PCI Bridge XIO2001 (Texas Instruments) User configurable FPGA TXMC639-10R: XC7K160T-2FBG676I (AMD) TXMC639-11R: XC7K325T-2FBG676I (AMD) SPI-Flash MT25QL128 (Micron) 128 Mbit (contains TXMC639 FPGA BRD) or compatible; +3.3 V supply voltage DDR3 RAM MT41K256M16TW-107 (Micron) Board Configuration LCMXO2-7000HC (Lattice)

  • Page 11: Table 2-1 : Technical Specification

    P16 Rear I/O 114 pin Mezzanine Connector (Samtec – ASP-105885-01) Physical Data Power Requirements Depends on FPGA design With TXMC639 Board Reference Design / without external load typical @ +12 V VPWR typical @ +5 V VPWR TXMC639-10R 1.1 A 2.5 A...

  • Page 12: Handling And Operation Instruction

    3 Handling and Operation Instruction ESD Protection The TXMC639 is sensitive to static electricity. Packing, unpacking and all other handling of the TXMC639 has to be done in an ESD/EOS protected Area. Thermal Considerations Forced air cooling is required during operation. Without forced air cooling, damage to the device can occur.

  • Page 13: Pci Device Topology

    4 PCI Device Topology The TXMC639 consists of two FPGAs. Both FPGAs are designed as PCIe / PCI endpoint devices. One FPGA is the User FPGA ( ) which can be programmed with user defined FPGA code. The second FPGA Kintex takes control of on-board hardware functions of TXMC639 and also the configuration control of the User FPGA.

  • Page 14: User Fpga (Kintex Tm 7)

    Table 4-2 : PCI Configuration Registers 4.2.2 PCI BAR Overview Port Size Endian Space Prefetch Width Description (Byte) Mode (it) Little Local Configuration Register Space Little In-System Programming Data Space Table 4-3 : PCI BAR Overview TXMC639 User Manual Issue 1.0.2 Page 14 of 95...

  • Page 15: Local Configuration Register Space

    0xE8 ISP Command Register (SPI) 0xEC ISP Status Register (SPI) 0xF0 Reserved 0xF4 TXMC639 Board Temperature 0xF8 TXMC639 Serial Number 0xFC Firmware Version Register Table 4-4 : Local Configuration Register Space TXMC639 User Manual Issue 1.0.2 Page 15 of 95...

  • Page 16: In-System Programming Data Space

    Control and status register for ISP are located in the Local Configuration Register Space. The data register for direct FPGA ISP is also located in the Local Configuration Register Space. TXMC639 User Manual Issue 1.0.2 Page 16 of 95...

  • Page 17: Register Description

    5 Register Description User FPGA (Kintex The FPGA register description depends on the user application and is not part of this manual. TXMC639 User Manual Issue 1.0.2 Page 17 of 95...

  • Page 18: Bcc (Board Configuration Controller) Fpga

    DAC and ADC Control / Status Register – 0x00 The output voltage and input voltage ranges of the TXMC639 DAC outputs are set via DAC and ADC Control / Status Register, DAC Output Voltage Range Register and ADC Input Voltage Range Register.

  • Page 19: Table 5-1 : Dac Control And Status Register

     Controller is not in idle DAC_REF_IOBSY  Span-Configuration update is pending  Output Value update is pending  Internal synchronization is pending Table 5-1 : DAC Control and Status Register TXMC639 User Manual Issue 1.0.2 Page 19 of 95...

  • Page 20: Dac Output Voltage Range Register - 0X04

    00 : ±20.56 V diff. - (default value) ADC_REF0 01 : ±10.28 V diff. 0b00 10 : ±5.14 V diff. 11 : not used Table 5-3 : ADC Input Voltage Range Register TXMC639 User Manual Issue 1.0.2 Page 20 of 95...

  • Page 21: Reference Dac Voltage Control Register - 0X10 To 0X4C

    DAC channel. Both reference voltages are each set as 16 bit value via a 32 bit register of the BCC. This results in 8 32 bit registers via which the reference voltage and thus the output voltage range of the TXMC639 can be configured.

  • Page 22: Table 5-5 : Voltage Coding For The Reference Dac

    Thus, any desired output voltage can be generated. But in any case it is important to ensure that the voltages VOUT and VREF are never set above +10 V or below -10 V. Voltages above these limits cannot be generated and lead to incorrect outputs. TXMC639 User Manual Issue 1.0.2 Page 22 of 95...

  • Page 23: Digital I/O Interface Configuration /Status Register - 0X60

    10 : pull-up to 3.3 V 01 : pull-up to 5 V 00 : No pull PULL_G0 I/O lines are summarized in the following groups. G0 = I/O_0 … I/O_15 G1 = I/O_16 … I/O_31 TXMC639 User Manual Issue 1.0.2 Page 23 of 95...

  • Page 24: Table 5-6 : I/O Pull-Resistor Configuration Register

    If the Pull-Resistors float, the user should keep in mind that the 16 I/O Lines of a group are connected via their Pull-Resistors. The default adjustment is that the BCC control the I/O Pull Configuration. TXMC639 User Manual Issue 1.0.2 Page 24 of 95...

  • Page 25: Txmc639 I/O Area Temperature Sensor Register - 0X64

    5.2.6 TXMC639 I/O Area Temperature Sensor Register - 0x64 Reset Symbol Description Access Value 31:21 Reserved TMP441 Automatic Temperature Read Enable Controls the periodic board temperature read feature. Refresh time = 1 s TMP441_AUTO _TRD_EN ‘0’ = disabled ‘1’ = enabled...

  • Page 26: User Fpga Jtag Control And Status Register - 0X80

    Hardwired JTAG interface from Debug 0b001 Connector to is active. Kintex 0b010 reserved BCC internal JTAG Controller is connected 0b100 Kintex Table 5-8 : User FPGA JTAG Control and Status Register TXMC639 User Manual Issue 1.0.2 Page 26 of 95...

  • Page 27: User Fpga Jtag Signal Line Register - 0X84

    Reserved JTAG Vector-I/O Enable Controls the state of the BCC JTAG Vector-I/O Interface. JTAG_VIO_EN- 0b0 = Vector-I/O disabled 0b1 = Vector-I/O enabled Functionality is held in reset until enabled is set TXMC639 User Manual Issue 1.0.2 Page 27 of 95...

  • Page 28: User Fpga Jtag Tms Data Register - 0X88

    Sets the JTAG TDI bit data that is shifted-out JTAG_VIO_TDI 31:0 during TMS/TDI shift operations. _DATA Note: bit 0 is shifted-out first (right-alignment) Table 5-11 : User FPGA JTAG TDI Data Register TXMC639 User Manual Issue 1.0.2 Page 28 of 95...

  • Page 29: User Fpga Jtag Tdo Data Register - 0X90

    0: Interrupt Disabled 1: Interrupt Enabled ISP_DAT_IE While disabled, the corresponding bit in the Interrupt Status Register is ‘0’. Disabling interrupts does not affect the interrupt source. Table 5-14 : Interrupt Enable Register TXMC639 User Manual Issue 1.0.2 Page 29 of 95...

  • Page 30: Interrupt Status Register - 0Xc4

    When set, the PCI INTA# interrupt is asserted. ISP_DAT_IS The Interrupt is cleared by writing a ‘1’. 0: Interrupt not active or disabled 1: Interrupt active and enabled Table 5-15 : Interrupt Status Register TXMC639 User Manual Issue 1.0.2 Page 30 of 95...

  • Page 31: User Fpga Configuration Control/Status Register - 0Xd0

    1: Slave SelectMap (Parallel) FP_CFG_MD After power-up the User FPGA automatically configures from the on-board SPI Flash in ‘Master Serial / SPI’ mode. Table 5-16 : User FPGA Configuration Control/Status Register TXMC639 User Manual Issue 1.0.2 Page 31 of 95...

  • Page 32: User Fpga Configuration Data Register - 0Xd4

    ‘Master Serial / SPI’ mode. Note, that for ISP Direct FPGA Programming, the FPGA must first be set to Slave Select Map configuration mode. Table 5-18 : ISP Control Register TXMC639 User Manual Issue 1.0.2 Page 32 of 95...

  • Page 33: Isp Configuration Register - 0Xe4

    ISP Status Register and starts the configured SPI instruction. ISP_SPI_INS_CMD Ignored (lost) while the Instruction Busy bit is set in the ISP Status Register. Always read as ‘0’. Table 5-20 : ISP Command Register TXMC639 User Manual Issue 1.0.2 Page 33 of 95...

  • Page 34: Isp Status Register - 0Xec

    (in read mode). Capable of generating an event based interrupt. 0: No ISP SPI Data Transfer in Progress 1: ISP SPI Data Transfer in Progress Table 5-21 : ISP Status Register TXMC639 User Manual Issue 1.0.2 Page 34 of 95...

  • Page 35: Txmc639 Board Temperature Sensor Register - 0Xf4

    5.2.15 TXMC639 Board Temperature Sensor Register - 0xF4 Reset Symbol Description Access Value 31:21 Reserved TMP441 Automatic Temperature Read Enable Controls the periodic board temperature read feature. Refresh time = 1s TMP441_AUTO _TRD_EN ‘0’ = disabled ‘1’ = enabled Automatic mode must be disabled before...

  • Page 36: Interrupts

    Both Interrupts of the BCC must be cleared via write access to the corresponding Interrupt Status Flag in the Interrupt Status Register (active-high write clear). TXMC639 User Manual Issue 1.0.2 Page 36 of 95...

  • Page 37: Functional Description

    7 Functional Description User FPGA Block Diagram Figure 7-1 : FPGA Block Diagram For pin assignment, I/O standard, slew rate and driver performance please use the XDC files of the TXMC639 BRD Project. TXMC639 User Manual Issue 1.0.2 Page 37 of 95...

  • Page 38: User Fpga Highlights

    11,700 -11R XC7K325T 326,080 50.950 16,020 Table 7-1 : TXMC639 FPGA Feature Overview PCI Express Highlights:  Compliant to the PCI Express Base Specification 2.1 with Endpoint and Root Port capability.  Supports Gen1 (2.5 Gb/s) and Gen2 (5 Gb/s)

  • Page 39: User Fpga Gigabit Transceiver (Mgt)

    User FPGA Gigabit Transceiver (MGT) The TXMC639 provides four MGT as Kintex 7 PCI Express Endpoint Block and four MGT for a high speed XMC P16 Rear I/O interface. Figure 7-2 : User FPGA MGT Block Diagram TXMC639 Signal FPGA Pins...

  • Page 40: Table 7-4 : User Fpga Mgt Reference Clocks

    The MGT clock MGTREFCLK0_116 (PCI Express Endpoint Block clock reference) of 100 MHz is generated by the PI7C9X2G312GP PCIe Switch. The MGTREFCLK0_115 is connected to a 125 MHz clock output of the Si5338 low jitter clock generator. MGTREFCLK1_115 and MGTREFCLK1_116 are not used on the TXMC639. TXMC639 Signal...

  • Page 41: User Fpga Configuration

    All required general settings, bitstream setting and additional constraints for a compressed tandem SPI X4 configuration could be found in the TXMC639 Board Reference Design application. Note: Changing a configuration to tandem configuration results in a change in the timing of the design.

  • Page 42: Manually User Fpga Spi Flash Reconfiguration

    If the PCIe interface of the User FPGA PCIe Endpoint does not change. Device ID, Vendor ID, Class Code and PCI Bars do not change, the PCI header could be saved before the FPGA Reconfiguration and written back to configuration space after the Reconfiguration. TXMC639 User Manual Issue 1.0.2 Page 42 of 95...

  • Page 43: Slave Select Map Configuration

    1: FPGA DONE Pin Level is High (FPGA is configured) After reconfiguration was successful the User FPGA Configuration Mode and the ISP Mode could be disabled. Also the link between the PCIe Switch and the Kintex 7 must be enabled. TXMC639 User Manual Issue 1.0.2 Page 43 of 95...
  • Page 44 This is also a binary configuration data file but without header information. For configuration of the Kintex 7 FPGA on the TXMC639 both files could be used. Both binary configuration data files have additional data to the actual configuration data.

  • Page 45: Configuration Via Jtag

    7.4.4 Configuration via JTAG The TXMC639 provides two JTAG chains which are accessible by the following connector options: 7.4.4.1 User JTAG Chain For direct FPGA configuration, FPGA read back or in-system diagnostics with Vivado Logic Analyzer, the Molex Debug Connector can be used to access the JTAG-chain. Also an indirect SPI – PROM programming is possible via the User JTAG Chain.

  • Page 46: Programming User Fpga Spi Configuration Flash

    The Programming Instruction always starts at address 0x00 to write data from the ISP Programming Data Space to the SPI flash. If not all configuration data bytes are written, the User FPGA is not configured correctly. TXMC639 User Manual Issue 1.0.2 Page 46 of 95...

  • Page 47: Erasing User Fpga Spi Configuration Flash

    After completion of the erasing process, the ISP Mode bit should be cleared to set configuration path to User FPGA or a User FPGA SPI Configuration Flash Set FP_CFG_MD = 0 programming process could be done. Set ISP_ENA = 0 TXMC639 User Manual Issue 1.0.2 Page 47 of 95...

  • Page 48: Sector Erasing User Fpga Spi Configuration Flash

    After completion of the erasing process, the ISP Mode bit should be cleared to set configuration path to User FPGA or a User FPGA SPI Configuration Flash programming process could be done. Set FP_CFG_MD = 0 Set ISP_ENA = 0 TXMC639 User Manual Issue 1.0.2 Page 48 of 95...

  • Page 49: Reading User Fpga Spi Configuration Flash

    Next Page ? After completion of the reading process, the ISP Mode bit must be cleared Set FP_CFG_MD = 0 to set configuration path back to User FPGA. Set ISP_ENA = 0 TXMC639 User Manual Issue 1.0.2 Page 49 of 95...

  • Page 50: Bcc (Board Configuration Controller) Fpga

    The Board Configuration FPGA is factory configured, and handles the basic board setup and User FPGA (Kintex 7) Configuration. Changing or erasing the BCF (Board Configuration Firmware) content leads to an inoperable TXMC639 FPGA configuration. 7.5.1 I2C Interface to BCC Register The TXMC639 BCC provides an I2C Interface to the User FPGA (Kintex 7).

  • Page 51: Clocking

    Clocking 7.6.1 FPGA Clock Sources As a central clock generator of the TXMC639 the Si5338 clock generator is used. This provides all necessary clocks for the User FPGA and the Configuration FPGA. The following figure depicts an abstract User FPGA clock flow.

  • Page 52: Table 7-6 : Available Fpga Clocks

    The following table lists the available clock sources on the TXMC639: FPGA Clock Signal FPGA Pin Source Description Name 125 MHz differential SI5338 low-jitter clock CLK_MGT± H6 / H5 MGT Reference clock for P16 generator Rear I/O Interface 100 MHz differential PCIe Switch REFCLKO2±...

  • Page 53: Serial Adc Interface

    Serial ADC Interface 7.7.1 Overview The 16 analog inputs of the TXMC639 are realized with 2 LTC2320-16 ADC devices. Each of these SAR- ADCs has eight ADC channels. Thus, a total of 16 ADC channels are available on the TXMC639.

  • Page 54: Adc Digital Output Coding

    VIN- and VIN+. An Example: The TXMC639 (differential input) voltage range is ±20.56 V, so the allowed (single-ended, ground related) voltage on each ADC input pin is ±10.28 V. When we examine the two largest differential voltages,...

  • Page 55: Adc Data Coding ±10.28 V Voltage Range

    Least Significant bit 157 µV Full Scale (pos.) 5.14 V 0x7FFF Midscale + 1LSB 157 µV 0x0001 Midscale 0.0 V 0x0000 Midscale – 1LSB -157 µV 0xFFFF Full Scale (neg.) -5.14 V 0x8000 TXMC639 User Manual Issue 1.0.2 Page 55 of 95...

  • Page 56: User Fpga Pinning

    To use the clocked serial interface between the User FPGA (Kintex 7) and one of the two LTC2320-16 ADC devices please use the LTC2320-16 data sheet which describes the communication process. TXMC639 User Manual Issue 1.0.2 Page 56 of 95...

  • Page 57: Programming Hints Ltc2320-16

    For the SCK± an external termination resistor is implemented on the TXMC639. The User FPGA inputs ADC_CLKOUT±, SDOA1±, SDOB±, SDOC± and SDOD± of each ADC channel need an FPGA internal termination. The corresponding constrains for the pin assignment, the I/O standard, termination and slew rate is specified in BRD XDC File.

  • Page 58: Parallel Dac Interface

    Capacitive Load Driving = 1000 pF 7.8.2 Output Voltage Range The output voltage ranges of the TXMC639 DAC outputs are set via BCC Register - DAC Control / Status Register and DAC Output Voltage Range Register. There are three predefined output voltage ranges ±10 V, ±5 V, ±2,5 V and a fourth mode in which the high and low voltage range can be set individually.

  • Page 59: User Fpga Pinning

    DAC_MSB = 1 corresponds to midscale reset Table 7-9: TXCM639 parallel DAC Interface For pin assignment, I/O standard, slew rate and driver performance please use the XDC files of the TXMC639 BRD Project. TXMC639 User Manual Issue 1.0.2 Page 59 of 95...

  • Page 60: Programming Hints For Ad5547

    7.8.4 Programming Hints for AD5547 TXMC639 DAC Channel write to DAC Input Register Decoding. ADR0 'WR00_01' 'WR02_03' 'WR04_05' 'WR06_07' DAC Channel Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Channel 8 TXMC639 DAC Channel LOAD_DAC Register Decoding.

  • Page 61: Ttl I/O Interface

    Due to on placement restrictions, groups are needed for the pull voltage. If the Pull-Resistors are set to float (possible selection), the user should keep in mind that the I/O Lines of one group are connected via their Pull-Resistors. TXMC639 User Manual Issue 1.0.2 Page 61 of 95...

  • Page 62: User Fpga Pinning

    3.3 V IN/OUT TTL_IO<31> 3.3 V IN/OUT TTL_OE<0> AA25 3.3 V OUTPUT TTL_OE<1> 3.3 V OUTPUT TTL_OE<2> 3.3 V OUTPUT TTL_OE<3> 3.3 V OUTPUT TTL_OE<4> 3.3 V OUTPUT TTL_OE<5> 3.3 V OUTPUT TXMC639 User Manual Issue 1.0.2 Page 62 of 95...

  • Page 63: Table 7-10 : User Fpga Ttl Io And Oe Pins

    OUTPUT Table 7-10 : User FPGA TTL IO and OE Pins For pin assignment, I/O standard, slew rate and driver performance please use the XDC files of the TXMC639 BRD Project. TXMC639 User Manual Issue 1.0.2 Page 63 of 95...

  • Page 64: Rs422 Interface

    RS422 Interface The TXMC639 provides a multiplex functionality between TTL and RS422 for 16 of the 32 ESD-protected TTL lines so that 16 TTL can alternatively be 8 RS422 channels. The 16 IO lines IO16 to IO31 become the 8 differential RS422 channels IO16_A/B to IO23_A/B.

  • Page 65: User Fpga Pinning

    2.5 V RS_DE<6> 2.5 V RS_DE<7> 2.5 V Diver Input RS_DI<0> 2.5 V RS_DI<1> 2.5 V RS_DI<2> 2.5 V RS_DI<3> 2.5 V RS_DI<4> 2.5 V RS_DI<5> 2.5 V RS_DI<6> 2.5 V TXMC639 User Manual Issue 1.0.2 Page 65 of 95...

  • Page 66: Table 7-11 : User Fpga Rs422 Interface Pins

    RS_TE<7> 3.3 V Table 7-11 : User FPGA RS422 Interface Pins For pin assignment, I/O standard, slew rate and driver performance please use the XDC files of the TXMC639 BRD Project. TXMC639 User Manual Issue 1.0.2 Page 66 of 95...

  • Page 67: I/O Pull Configuration

    The BCC offers an additional option for setting the I/O Pull voltage. Through its Digital I/O Interface Configuration / Status Register the User FPGA control can be revoked or rather dominated. (Use this Register to set the desired pull resistor reference.) TXMC639 User Manual Issue 1.0.2 Page 67 of 95...

  • Page 68: Memory

    Memory The TXMC639 is equipped with a 1 GB, 32 bit wide DDR3 SDRAM and a 128 Mbit non-volatile SPI-Flash. The SPI-Flash can also be used as the User FPGA configuration memory. 7.12.1 DDR3 SDRAM The TXMC639 provides one MT41… (96-ball) DDR3 memory devices. The memory is accessible through a Memory Interface Controller Block IP in bank 33 and 34 of the User FPGA.

  • Page 69: Table 7-14 : Ddr3 Sdram Interface

    F3 / G3 LDQS± DQS_3± AF5 / AF4 C7 / B7 UDQS± Table 7-14 : DDR3 SDRAM Interface DDR3 Memory Device 01 DDR3 Memory Device 02 Both DDR3 Memory Devices 01 & 02 TXMC639 User Manual Issue 1.0.2 Page 69 of 95...
  • Page 70 TXMC639 BRD Project. For details regarding the DDR3 SDRAM interface, please refer to AMD Memory Interface Generator Documentation. AMD UG586: Zynq-7000 AP SoC and 7 Series Devices Memory Interface Solutions v4.2. TXMC639 User Manual Issue 1.0.2 Page 70 of 95...

  • Page 71: Spi-Flash

    7.12.2 SPI-Flash The TXMC639 provides a Micron MT25QL128ABA 128 Mbit serial Flash memory. This Flash is used as FPGA configuration source (default configuration source). After configuration, it is always accessible from the FPGA, so it also can be used for code or user data storage.

  • Page 72: Adc And Dac Ccorrectable Errors

    0x03D ADC Channel 15, Offset Low Byte Corr 0x03E ADC Corretion 15, Gain High Byte Corr 0x03F ADC Corretion 15, Gain Low Byte Corr 0x040 .. 0x07E Reserved ADC Range 1 TXMC639 User Manual Issue 1.0.2 Page 72 of 95...

  • Page 73: Table 7-17: Adc Correction Values

    ADC Channel 15, Offset Low Byte Corr 0x13E ADC Corretion 15, Gain High Byte Corr 0x13F ADC Corretion 15, Gain Low Byte Corr 0x140 .. 0x67F Reserved Table 7-17: ADC Correction Values TXMC639 User Manual Issue 1.0.2 Page 73 of 95...

  • Page 74: Dac Corretion Values

    DAC Range 2 0x700 DAC Range 2 Channel 0 Offset High Byte corr 0x701 DAC Range 2 Channel 0 Offset Low Byte corr 0x702 DAC Range 2 Channel 0 Gain High Byte corr TXMC639 User Manual Issue 1.0.2 Page 74 of 95...

  • Page 75: Table 7-18: Dac Correction Data Values

    0x71E DAC Range 2 Channel 7 Offset High Byte corr 0x71F DAC Range 2 Channel 7 Offset Low Byte corr 0x720 .. 0x73E Reserved Table 7-18: DAC Correction Data Values TXMC639 User Manual Issue 1.0.2 Page 75 of 95...

  • Page 76: Adc Data Correction Formula

    7.12.3.4 ADC Data Correction Formula Please use the total 16 bit data register value for the ADC correction formula. The basic formula for correcting any ADC reading for the TXMC639 (bipolar input voltage range) is:   Gain Offset ...

  • Page 77: Dac And Adc Voltage Ranges

    0x76F DAC Output Range 1, Channel 7 Low Byte 0x770 .. 0x77F Reserved 0x780 DAC Output Range 2, Channel 0 High Byte 0x781 DAC Output Range 2, Channel 0 Low Byte TXMC639 User Manual Issue 1.0.2 Page 77 of 95...
  • Page 78 ACD Input Voltage Range 1, Channel 6 + 7 High Byte 0x7C7 ACD Input Voltage Range 1, Channel 6 + 7 Low Byte 0x7C8 ACD Input Voltage Range 1, Channel 8 + 9 High Byte TXMC639 User Manual Issue 1.0.2 Page 78 of 95...

  • Page 79: Version Of Eeprom Data Structure

    Table 7-19: ADC and DAC voltage ranges 7.12.3.7 Version of EEPROM data structure In the first versions of TXMC639 only the correction data were stored. A version register is used to identify whether the voltage ranges are also present. I2C EEPROM...

  • Page 80: Rear I/O Interface

    Rear I/O Interface The Rear I/O Pins of the TXMC639 are directly routed to the User FPGA (Kintex 7). The I/O functions of these FPGA pins are directly dependent on the configuration of the FPGA. The Kintex 7 VCCO voltage is set to 2.5 V, so only the 2.5 V I/O standards LVCMOS25, LVTTL25 and LVDS_25 are possible when using the TXMC639 rear I/O interface.

  • Page 81: Table 7-21 : Digital Rear I/O Interface

    LVDS_25 REAR_IO31+ IN/OUT LVDS_25 Table 7-21 : Digital Rear I/O Interface For pin assignment, I/O standard, slew rate and driver performance please use the XDC files of the TXMC639 BRD Project. TXMC639 User Manual Issue 1.0.2 Page 81 of 95...

  • Page 82: Digital Interface To Xmc P16 Connector

    The I/O functions of these FPGA pins are directly dependent on the configuration of the User FPGA. The Kintex 7 VCCO voltage for these pins is set to 2.5 V, so only the 2.5 V I/O standards LVCMOS25, LVTTL25 and LVDS25 are possible when using this TXMC639 XMC P16 Rear I/O interface. IO Standard Signal Name...

  • Page 83: Jtag Controller To User Fpga Jtag Interface

    TMS/TDI operation. Read-in updates appear immediately on the JTAG Vector-I/O TDO data vector (JTAG_VIO_TDO_DATA). Note that bit #0 is the last one that has been read-in from the JTAG interface. TXMC639 User Manual Issue 1.0.2 Page 83 of 95...

  • Page 84: I2C Bridge

    Channel 4 must be 3.3 V SSTL on A and B Do not change Si5338 Core VDD or I2C Bus Voltage Core VDD = 3.3 V I2C Bus Voltage = 2.5 V or 3.3 V TXMC639 User Manual Issue 1.0.2 Page 84 of 95...

  • Page 85: On-Board Indicators

    On-Board Indicators The TXMC639 provides a couple of board-status LEDs as shown below. These include Power-Good and FPGA configuration status indications as well as two general purpose LEDs. Color State Description On-Board Power Supplies Green are all ok Power Good Power Good Signal for all on-board power supplies.

  • Page 86: User Fpga Led Pinning

    USER_LED0 3.3 V 2x green on-board LEDs USER_LED1 Table 7-24: TXMC639 User On-Board Indicators For pin assignment, I/O standard, slew rate and driver performance please use the XDC files of the TXMC639 BRD Project. User FPGA Reset Inputs General purpose Reset input connected to the User FPGA Kintex...

  • Page 87: Design Help

    8 Design Help Board Reference Design User applications for the TXMC639 may be developed by using the TXMC639 FPGA Board Reference Design. TEWS offers this Board Reference Design as a well-documented basic example. It includes an .xdc constrain file with all necessary pin assignments and basic timing constraints. The example design covers the main functionalities of the TXMC639.

  • Page 88: O Interfaces

    Maximum VIN = ±20.56 V Maximum VIN = ±20.56 V The TXMC639 has differential analog inputs. When talking about the input voltage range of a differential input, one has to differentiate between the differential input voltage between the two pins, and the input voltage relative to ground for each pin.

  • Page 89: Front I/O - Analog Output Level

    Description. 9.1.3 Rear I/O Interface All 64 single-ended / 32 differential digital rear I/O Pins of the TXMC639 are directly routed from the User FPGA (Kintex 7) to the 64 pin P14 XMC rear connector. The I/O functions of these FPGA pins are directly dependent on the configuration of the FPGA.

  • Page 90: O Description

    10 I/O Description Overview TXMC639 User Manual Issue 1.0.2 Page 90 of 95...

  • Page 91: Front I/O Connector (X1)

    ADC_IN1+ ADC_IN0- ADC_IN1- ADC_IN2+ ADC_IN3+ ADC_IN2- ADC_IN3- ADC_IN4+ ADC_IN5+ ADC_IN4- ADC_IN5- ADC_IN6+ ADC_IN7+ ADC_IN6- ADC_IN7- ADC_IN8+ ADC_IN9+ ADC_IN8- ADC_IN9- ADC_IN10+ ADC_IN11+ ADC_IN10- ADC_IN11- ADC_IN12+ ADC_IN13+ ADC_IN12- ADC_IN13- ADC_IN14+ ADC_IN15+ ADC_IN14- ADC_IN15- TXMC639 User Manual Issue 1.0.2 Page 91 of 95...

  • Page 92: Table 10-1: Pin Assignment Front Panel I/O Connector

    RS422_2A TTL_IO22 RS422_3A TTL_IO21 RS422_2B TTL_IO23 RS422_3A TTL_IO24 RS422_4A TTL_IO26 RS422_5A TTL_IO25 RS422_4B TTL_IO27 RS422_5B TTL_IO28 RS422_6A TTL_IO30 RS422_7A TTL_IO29 RS422_6B TTL_IO31 RS422_7B Table 10-1: Pin Assignment Front Panel I/O Connector TXMC639 User Manual Issue 1.0.2 Page 92 of 95...

  • Page 93: Rear I/O Connector (P14)

    IO_R_29+ IO_R_58 IO_R_13- IO_R_27 IO_R_29- IO_R_59 IO_R_14+ IO_R_28 IO_R_30+ IO_R_60 IO_R_14- IO_R_29 IO_R_30- IO_R_61 IO_R_15+ IO_R_30 IO_R_31+ IO_R_62 IO_R_15- IO_R_31 IO_R_31- IO_R_63 Figure 10-2 : Pin Assignment P14 Rear I/O Connector TXMC639 User Manual Issue 1.0.2 Page 93 of 95...

  • Page 94: Rear I/O Connector (P16)

    Rx 0- Rx 1+ Rx 1- Rx 2+ Rx 2- Rx 3+ Rx 3- DIG_IO_02- DIG_IO_03- DIG_IO_02+ DIG_IO_03+ DIG_IO_00- DIG_IO_01- DIG_IO_00+ DIG_IO_01+ Figure 10-3 : Pin Assignment P16 Rear I/O Connector TXMC639 User Manual Issue 1.0.2 Page 94 of 95...

  • Page 95: Fpga Jtag Header (X2)

    Test Data Input (TAP Controller: TDO) not connected on the TXMC639 not connected on the TXMC639 PGND Used on TXMC639 for AMD Header present detection HALT_INIT_WP signal. Optional. Not connected on the TXMC639 Table 10-2: Pin Assignment JTAG Header TXMC639 User Manual Issue 1.0.2...

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