1. Manuals
  2. Brands
  3. Tews Technologies Manuals
  4. I/O Systems
  5. TPMC634 Series
  6. User manual

Tews Technologies TPMC634 Series User Manual

Re-configurable fpga with 64 ttl i/o / 32 differential i/o
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
The Embedded I/O Company
TPMC634
Re-Configurable FPGA with
64 TTL I/O / 32 Differential I/O
Version 1.0
User Manual
Issue 1.0.1
April 2018
TEWS TECHNOLOGIES GmbH
Am Bahnhof 7
25469 Halstenbek, Germany
Phone: +49 (0) 4101 4058 0
Fax: +49 (0) 4101 4058 19
e-mail:
info@tews.com
www.tews.com

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the TPMC634 Series and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for Tews Technologies TPMC634 Series

Summary of Contents for Tews Technologies TPMC634 Series

  • Page 1 Re-Configurable FPGA with 64 TTL I/O / 32 Differential I/O Version 1.0 User Manual Issue 1.0.1 April 2018 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek, Germany Phone: +49 (0) 4101 4058 0 Fax: +49 (0) 4101 4058 19 e-mail: info@tews.com...
  • Page 2 TPMC634-12R in this document at any time without notice. Re-Configurable FPGA with 16 Differential TEWS TECHNOLOGIES GmbH is not liable for any EIA-422 / EIA-485 I/O and 32 TTL I/O damage arising out of the application or use of the device described herein.
  • Page 3 Issue Description Date 1.0.0 Initial Issue April 2015 1.0.1 Order Option Description unified April 2018 TPMC634 User Manual Issue 1.0.1 Page 3 of 93...

  • Page 4: Table Of Contents

    Table of Contents PRODUCT DESCRIPTION ................... 9 TECHNICAL SPECIFICATION ................... 11 HANDLING AND OPERATION INSTRUCTIONS ............13 ESD Protection ..........................13 User FPGA Power Dissipation Limit ................... 13 I/O Interface Installation ....................... 13 Default TTL I/O Line States ......................13 Pre-Installed User FPGA Example ....................
  • Page 5 USER PROGRAMMABLE FPGA CONFIGURATION ..........42 User FPGA Configuration Options ....................42 FPGA Configuration from SPI Flash ................... 42 7.2.1 Auto-Configuration at Power-Up ..................... 42 7.2.2 SW Controlled Re-Configuration .................... 42 7.2.3 SPI Flash Preparation ......................43 7.2.4 FPGA Configuration Time ....................... 43 FPGA Configuration via PCI/Software ..................
  • Page 6 14 I/O INTERFACE ......................75 14.1 General I/O Interface Description ....................75 14.1.1 Single-Ended I/O Line Interface ....................75 14.1.2 Differential I/O Line Interface ....................77 14.2 I/O Connectors ..........................78 14.2.1 Front-I/O Connector Part Number ..................78 14.2.2 Rear-I/O Connector Part Number ................... 78 14.3 I/O Line Signal Level ........................
  • Page 7 List of Figures FIGURE 1-1 : TPMC634 BLOCK DIAGRAM ....................10 FIGURE 4-1 : PCI HEADER ..........................15 FIGURE 9-1 : LOCAL BUS SIGNAL PROTOCOL EXAMPLE DIAGRAMS ........... 68 FIGURE 11-1: LED LOCATION ........................71 FIGURE 12-1: JTAG HEADER PIN ORDER ....................72 FIGURE 12-1: JTAG HEADER LOCATION ....................
  • Page 8 TABLE 11-1: ON-BOARD LEDS ........................71 TABLE 12-1: JTAG HEADER PART NUMBER ....................72 TABLE 12-2: JTAG HEADER PIN ASSIGNMENT ..................72 TABLE 13-1: 4-POS. ROTARY SWITCH CONFIGURATION ................ 74 TABLE 14-1 : FRONT I/O CONNECTOR PART NUMBER ................78 TABLE 14-2: REAR I/O CONNECTOR PART NUMBER ................

  • Page 9: Product Description

    1 Product Description The TPMC634 is a standard single-width 32 bit PMC module providing a user programmable FPGA with front-I/O and P14 rear-I/O. The TPMC634 provides a 32 bit 33MHz PCI Target interface. A dedicated (FPGA based) PCI Target Chip is used as a target bridge between the PCI bus and an on-board off-chip local bus.

  • Page 10: Figure 1-1 : Tpmc634 Block Diagram

    Figure 1-1 : TPMC634 Block Diagram TPMC634 User Manual Issue 1.0.1 Page 10 of 93...

  • Page 11: Technical Specification

    2 Technical Specification PMC Interface Mechanical Interface PCI Mezzanine Card (PMC) Interface confirming to IEEE P1386/P1386.1 Single Size Electrical Interface PCI Rev. 3.0 compatible 33 MHz / 32 bit PCI Minimum PCI Clock Frequency is 8 MHz 3.3V and 5V PCI Signaling Voltage On-Board Devices PCI Target Chip (FPGA) Lattice MachXO2 LCMXO2-4000HE-5BG320I...

  • Page 12: Table 2-1 : Technical Specification

    MTBF TPMC634-10R: 423000 h TPMC634-11R: 440000 h TPMC634-12R: 431000 h TPMC634-13R: 429000 h TPMC634-14R: 425000 h MTBF values shown are based on calculation according to MIL-HDBK-217F and MIL-HDBK-217F Notice 2; Environment: G 20°C. The MTBF calculation is based on component FIT rates provided by the component suppliers.

  • Page 13: Handling And Operation Instructions

    3 Handling and Operation Instructions ESD Protection The PMC module is sensitive to static electricity. Packing, unpacking and all other module handling has to be done with the appropriate care. User FPGA Power Dissipation Limit The absolute maximum junction temperature of the Xilinx Spartan-6 XC6SLX25-2FGG484I is +125°C and must not be exceeded.

  • Page 14: Pre-Installed User Fpga Example

    Pre-Installed User FPGA Example The TPMC634 comes with a factory default User FPGA Example application stored in the on-board SPI Flash. After power-up, the Spartan-6 User FPGA is automatically configured with the User FPGA Example application. The User FPGA Example application provides registers for enabling the TPMC634 I/O line drivers! Care must be taken, not to write accidently data to the registers implemented by the User FPGA Example application!

  • Page 15: Pci Target Interface

    Config. Pre- Description Configured Reg. Values 24 23 16 15 Offs. Device ID Vendor ID 0x00 0x027A1498 (TPMC634) (TEWS Technologies) 0x04 Status Command 0x08 Class Code Revision ID 0x11800001 BIST Latency Timer Cache Line Size 0x0C Header Type not supported...

  • Page 16: Pci Bar Overview

    PCI BAR Overview Port Size Prefetch- Endian Width Description Space (Byte) able Mode (Bit) PCI Target Register Little Space In-System Little Programming Space (SPI Flash) 256K Optional User Space 0 by default, Little Enabled by factory default 16M max Disabled Optional User Space 1 by default, Little...

  • Page 17: Pci Configuration Eeprom Parameter

    PCI Configuration EEPROM Parameter The following PCI configuration space parameters are loaded from an on-board serial EEPROM after PCI reset. Serial Default Fallback EEPROM Value Value Parameter Word (Default (Invalid EEPROM) EEPROM) Offset PCI Configuration Space Parameter 0x00 Device ID 0x027A 0x027A 0x01...

  • Page 18: Pci Clock Frequency

    PCI Clock Frequency The TPMC634 provides a 32 bit 33 MHz PCI Target Interface. The minimum PCI clock frequency is 8 MHz (lower PCI clock frequencies are not supported). PCI Access Times The following table shows the approximate TPMC634 PCI access times. Two PCI bus idle cycles after each PCI access (and between delayed read retries) and 0 address wait states, 1 data wait state on the local bus are assumed.

  • Page 19: Address Maps

    5 Address Maps PCI Target Register Space PCI BAR 0 implements the Configuration Registers located within the PCI Target Device. Offset to Register Name PCI BAR 0x90 Local Bus Interface Control / Status Register 0x94 Reserved 0x98 Reserved 0x9C Reserved 0xA0 Reserved (I/O Interface Control / Status Register) 0xA4...

  • Page 20: Local Bus Interface Register (0X90)

    5.1.1 Local Bus Interface Register (0x90) Reset Symbol Description Access Value Event Flags 31:27 Reserved Local Bus PLL Loss-of-Lock Flag Set by HW when the local bus clock PLL lock status has changed from locked to not-locked LB_PLL_LOS Only functional for PLL based local bus clock implementation options Write ‘1’...

  • Page 21: Configuration Eeprom Register (0Xb0)

    Local Bus Reset 0: No SW controlled local bus reset LB_RST 1: SW controlled local bus reset Table 5-2 : Local Bus Interface Register 5.1.1 Configuration EEPROM Register (0xB0) Reset Symbol Description Access Value Configuration EEPROM Instruction Go / Busy Status Setting this bit starts performing the configured EEPROM instruction.

  • Page 22: Interrupt Enable Register (0Xc0)

    5.1.2 Interrupt Enable Register (0xC0) Reset Symbol Description Access Value 31:8 Reserved Local Bus Interrupts Reserved Local Bus Error Interrupt Enable 0: Interrupt Disabled LB_ERR_IE 1: Interrupt Enabled Local Bus User Interrupt Enable LB_USR_IE 0: Interrupt Disabled 1: Interrupt Enabled ISP Interrupts Reserved ISP SPI Instruction Done Event Interrupt Enable...

  • Page 23: Interrupt Status Register (0Xc4)

    5.1.1 Interrupt Status Register (0xC4) Reset Symbol Description Access Value 31:8 Reserved Local Bus Interrupts Reserved Local Bus Error Interrupt Status 0: Interrupt Status = Clear 1: Interrupt Status = Set If enabled, the interrupt status is set when any of the following error events occurs: •...

  • Page 24: Interrupt Configuration Register (0Xc8)

    5.1.2 Interrupt Configuration Register (0xC8) Reset Symbol Description Access Value 31:1 Reserved Interrupt Acknowledge Mode 0: Interrupt Clear-by-Write Mode 1: Interrupt Clear-on-Read Mode Interrupt Clear-by-Write Mode: For both ISP based interrupts and for the Local Bus Error Interrupt, the interrupt status is cleared by writing a ‘1’...

  • Page 25: User Fpga Configuration Data Register (Slave Selectmap) (0Xd4)

    After clearing this bit, the SW should check the INIT_B signal status until it is read as ‘1’. After power-up the FPGA automatically attempts to configure from the on-board SPI Flash in ‘Master Serial / SPI’ mode User FPGA Configuration Mode Control 0: Master Serial / SPI (configuration from SPI Flash) 1: Slave SelectMAP x8 (volatile configuration via PCI FP_CFG_...

  • Page 26: Isp Control Register (Spi) (0Xe0)

    5.1.1 ISP Control Register (SPI) (0xE0) Reset Symbol Description Access Value 31:1 Reserved ISP Mode Enable 0: Disable ISP Mode 1: Enable ISP Mode This bit controls on-board analog multiplexers for signal connections between the MachXO2 FPGA, the ISP_EN User FPGA configuration interface and the on-board SPI Flash.

  • Page 27: Isp Status Register (Spi) (0Xec)

    ISP SPI Start Instruction Command Bit Writing a ‘1’ sets the SPI Instruction Busy Bit in the ISP Status Register and starts the configured SPI ISP_SPI_ instruction. INS_CMD Ignored (lost) while the Instruction Busy Bit is set in the ISP Status Register. Always read as ‘0’.

  • Page 28: Control & Status Register (0Xf0)

    5.1.1 Control & Status Register (0xF0) Reset Symbol Description Access Value 31:24 Reserved Reserved Control 23:17 Write as ‘0’ MXO LED Control MXO_LED 0: MXO LED Off 1: MXO LED On (Default) 15:4 Reserved Status DIP-Switch Setting The bits are reflecting the on-board DIP switch configuration (ON = 1, OFF = 0) DIP_SW...

  • Page 29: User Space(S)

    User Space(s) PCI BARs 2 to 5 are reserved for implementing optional user spaces. The TPMC634 supports up to four user spaces for accessing the user programmable Spartan-6 FPGA on the TPMC634 local bus. If enabled, user spaces must be used in ascending order. Each user space is assigned to a dedicated PCI BAR.

  • Page 30: User Programmable Fpga

    6 User Programmable FPGA FPGA Part The User FPGA on the TPMC634 is a Xilinx Spartan-6 XC6SLX25-2-FGG484I. The Xilinx Spartan-6 XC6SLX25 is supported by the Xilinx ISE WebPACK tool. The following table shows some key User FPGA resources. FPGA XC6SLX25 Resource Logic Cells 24051...
  • Page 31 Local Bus Interface Signals Drive Slew Signal Name Direction Standard Bank [mA] Rate LB_AD[3] AB10 LVCMOS33 SLOW LB_AD[4] LVCMOS33 SLOW LB_AD[5] LVCMOS33 SLOW LB_AD[6] LVCMOS33 SLOW LB_AD[7] LVCMOS33 SLOW LB_AD[8] LVCMOS33 SLOW LB_AD[9] LVCMOS33 SLOW LB_AD[10] LVCMOS33 SLOW LB_AD[11] LVCMOS33 SLOW LB_AD[12] LVCMOS33...

  • Page 32: I/O Interface Signals

    Local Bus Interface Signals Drive Slew Signal Name Direction Standard Bank [mA] Rate LB_BE#[0] LVCMOS33 LB_BE#[1] AA18 LVCMOS33 LB_BE#[2] AB18 LVCMOS33 LB_BE#[3] LVCMOS33 LB_RST# AB17 LVCMOS33 LB_CLK LVCMOS33 LB_CYC# AA21 LVCMOS33 LB_R/W# AA14 LVCMOS33 LB_D/A# AB14 LVCMOS33 LB_MRDY# LVCMOS33 LB_MABT# LVCMOS33 LB_TRDY# LVCMOS33...
  • Page 33 I/O Interface Signals Drive Slew Signal Name Direction Standard Bank [mA] Rate FPGA_IN[12] LVCMOS33 FPGA_IN[13] LVCMOS33 FPGA_IN[14] LVCMOS33 FPGA_IN[15] LVCMOS33 FPGA_IN[16] LVCMOS33 FPGA_IN[17] LVCMOS33 FPGA_IN[18] LVCMOS33 FPGA_IN[19] LVCMOS33 FPGA_IN[20] LVCMOS33 FPGA_IN[21] LVCMOS33 FPGA_IN[22] LVCMOS33 FPGA_IN[23] LVCMOS33 FPGA_IN[24] LVCMOS33 FPGA_IN[25] LVCMOS33 FPGA_IN[26] LVCMOS33 FPGA_IN[27]...
  • Page 34 I/O Interface Signals Drive Slew Signal Name Direction Standard Bank [mA] Rate FPGA_IN[45] LVCMOS33 FPGA_IN[46] LVCMOS33 FPGA_IN[47] LVCMOS33 FPGA_IN[48] LVCMOS33 FPGA_IN[49] LVCMOS33 FPGA_IN[50] LVCMOS33 FPGA_IN[51] LVCMOS33 FPGA_IN[52] LVCMOS33 FPGA_IN[53] LVCMOS33 FPGA_IN[54] LVCMOS33 FPGA_IN[55] LVCMOS33 FPGA_IN[56] LVCMOS33 FPGA_IN[57] LVCMOS33 FPGA_IN[58] LVCMOS33 FPGA_IN[59] LVCMOS33 FPGA_IN[60]...
  • Page 35 I/O Interface Signals Drive Slew Signal Name Direction Standard Bank [mA] Rate FPGA_OUT[14] LVCMOS33 SLOW FPGA_OUT[15] LVCMOS33 SLOW FPGA_OUT[16] LVCMOS33 SLOW FPGA_OUT[17] LVCMOS33 SLOW FPGA_OUT[18] LVCMOS33 SLOW FPGA_OUT[19] LVCMOS33 SLOW FPGA_OUT[20] LVCMOS33 SLOW FPGA_OUT[21] LVCMOS33 SLOW FPGA_OUT[22] LVCMOS33 SLOW FPGA_OUT[23] LVCMOS33 SLOW FPGA_OUT[24]...
  • Page 36 I/O Interface Signals Drive Slew Signal Name Direction Standard Bank [mA] Rate FPGA_OUT[47] LVCMOS33 SLOW FPGA_OUT[48] LVCMOS33 SLOW FPGA_OUT[49] LVCMOS33 SLOW FPGA_OUT[50] LVCMOS33 SLOW FPGA_OUT[51] LVCMOS33 SLOW FPGA_OUT[52] LVCMOS33 SLOW FPGA_OUT[53] LVCMOS33 SLOW FPGA_OUT[54] LVCMOS33 SLOW FPGA_OUT[55] LVCMOS33 SLOW FPGA_OUT[56] LVCMOS33 SLOW FPGA_OUT[57]...
  • Page 37 I/O Interface Signals Drive Slew Signal Name Direction Standard Bank [mA] Rate FPGA_OE[16] LVCMOS33 SLOW FPGA_OE[17] LVCMOS33 SLOW FPGA_OE[18] LVCMOS33 SLOW FPGA_OE[19] LVCMOS33 SLOW FPGA_OE[20] LVCMOS33 SLOW FPGA_OE[21] LVCMOS33 SLOW FPGA_OE[22] LVCMOS33 SLOW FPGA_OE[23] LVCMOS33 SLOW FPGA_OE[24] LVCMOS33 SLOW FPGA_OE[25] LVCMOS33 SLOW FPGA_OE[26]...

  • Page 38: Table 6-3 : I/O Interface Signals (Fpga Parameters)

    I/O Interface Signals Drive Slew Signal Name Direction Standard Bank [mA] Rate FPGA_OE[49] LVCMOS33 SLOW FPGA_OE[50] LVCMOS33 SLOW FPGA_OE[51] LVCMOS33 SLOW FPGA_OE[52] LVCMOS33 SLOW FPGA_OE[53] LVCMOS33 SLOW FPGA_OE[54] LVCMOS33 SLOW FPGA_OE[55] LVCMOS33 SLOW FPGA_OE[56] LVCMOS33 SLOW FPGA_OE[57] LVCMOS33 SLOW FPGA_OE[58] LVCMOS33 SLOW FPGA_OE[59]...

  • Page 39: Table 6-5 : Fpga I/O Interface Signal Usage For Tpmc634 Variants

    The FPGA_OE[63:0] signals are enabling or disabling the on-board I/O transmitters. All FPGA_OE[63:0] signals have an on-board pull-down resistor, disabling the I/O transmitters when the FPGA_OE pins are High-Z. See the I/O Interface chapter for more information. For the TPMC634-11R/-13R order options (differential I/O only) the FPGA_IN[63:32] signals are not used and not driven.

  • Page 40: Other User Signals

    6.3.3 Other User Signals Drive Slew Signal Name Direction Standard Bank [mA] Rate BAUD_CLK AB11 LVCMOS33 AUX_CLK AB13 LVCMOS33 Table 6-6 : Other User Signals The BAUD_CLK signal is a 7.3728 MHz clock signal that may be used to implement standard serial communication baud rates for the I/O interface.

  • Page 41: User Fpga Power Dissipation Limit

    MXO_S6_3 AA12 LB_CLK_OSC LB_REQ# LB_GNT# Table 6-7 : Reserved FPGA I/O Pins User FPGA Power Dissipation Limit The parts used on the TPMC634 are specified for industrial temperature range (-40°C… +85°C). The user must use appropriate design tools to ensure that the Spartan-6 FPGA junction temperature stays within the given limits for the actual environment and system conditions (maximum ambient temperature, system air flow / cooling) and the actual FPGA logic design.

  • Page 42: User Programmable Fpga Configuration

    7 User Programmable FPGA Configuration User FPGA Configuration Options The TPMC634 provides the following options for configuring the User FPGA. • FPGA Configuration from on-board SPI Flash (Master Serial / SPI FPGA Configuration Mode) The SPI Flash must be programmed accordingly before FPGA configuration. Either via the PCI bus or with the Xilinx iMPACT software and programmer cable via the TPMC634 JTAG header.

  • Page 43: Spi Flash Preparation

    3. Keep reading the User FPGA Configuration Control/Status Register (0xD0) until both bit 2 & 3 are clear I.e. wait until the Spartan-6 FPGA asserts the INIT_B and DONE pins low. 4. Write 0x00000000 to the User FPGA Configuration Control/Status Register (0xD0) This will release the Spartan-6 FPGA PROGRAM_B pin and will start the FPGA re-configuration in Master Serial / SPI configuration mode.

  • Page 44: Fpga Configuration Via Pci/Software

    FPGA Configuration via PCI/Software The TPMC634 supports direct (volatile) FPGA In-System-Programming via the PCI bus in Slave SelectMAP FPGA configuration mode (x8). 7.3.1 Configuration Data Files Programming the TPMC634 User FPGA directly in Slave SelectMAP configuration mode requires certain result files from the Xilinx ISE design flow. The .BIT file is a binary configuration data file containing header information that should not be programmed into the FPGA.
  • Page 45 .bit File Example Offset(h) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00000000 00 09 0F F0 0F F0 0F F0 0F F0 00 00 01 61 00 2B File Header 00000010 74 70 6D 63 36 33 34 5F 78 63 36 73 6C 78 32 35 00000020 5F 65 78 61 2E 6E 63 64 3B 55 73 65 72 49 44 3D...

  • Page 46: Direct Fpga Programming

    7.3.2 Direct FPGA Programming The registers used for direct (volatile) User FPGA In-System programming are located in the PCI Target Register Space. Steps for direct (volatile) User FPGA Programming (Software point-of-view) 1. Write 0x00000003 to the User FPGA Configuration Control/Status Register (0xD0) This will assert the Spartan-6 FPGA PROGRAM_B pin and will prepare a FPGA re-configuration in Slave SelectMAP configuration mode.

  • Page 47: Fpga Configuration Via Jtag Header

    Since the Spartan-6 Slave SelectMAP configuration port (x8) expects the configuration data bytes to be bit- swapped, each byte is automatically bit-swapped by HW when send to the Spartan-6 User FPGA configuration port. Therefore, the source configuration data set must be non-bit-swapped. It is recommended to use the Xilinx .BIN file format as the configuration data source file.
  • Page 48 11. Check successful Program operation and FPGA configuration 12. Check that the TPMC634 S6 LED is on and green now  The TPMC634 Xilinx XC6SLX25 Spartan-6 User FPGA is now configured TPMC634 User Manual Issue 1.0.1 Page 48 of 93...

  • Page 49: Spi Flash Programming

    8 SPI Flash Programming SPI Flash Notes The TPMC634 provides an on-board SPI Flash for storing the User FPGA configuration data. The SPI Flash is the default User FPGA configuration option after power-up. After Power-up, the Spartan-6 User FPGA always attempts to load the configuration bitstream from the on-board SPI Flash in Master Serial / SPI configuration mode.

  • Page 50: Xilinx Ise / Bitgen Options

    an SPI Flash Program operation only if SPI x4 mode has been selected in the Xilinx iMPACT flow configuration. So due to certain Xilinx iMPACT software operations, the non-volatile QE bit may get cleared, and once cleared, will stay so for subsequent power cycles. If the QE bit ever should get cleared by third party tools, measures must be taken to set the bit again in case SPI x4 mode is planned to be used for FPGA configuration from the SPI Flash in Master/Serial SPI configuration mode, especially if the new project configuration data is written to the SPI Flash via the PCI...

  • Page 51: Spi Flash Instructions

    Both the additional Spartan-6 configuration data and the main configuration data must be programmed into the SPI Flash page-wise via the ISP Space (PCI BAR 1) and the SPI Flash Page Program instruction. During the SPI Flash page program instruction, the bytes are transferred to the SPI Flash from lower to higher ISP Space (PCI BAR 1) byte addresses.

  • Page 52: Steps For Spi Flash Sector Erase Operation

    5. Write 0x00000000 to the ISP Control Register (0xE0) This will set the on-board configuration signal path so that the Spartan-6 User FPGA is connected to the SPI Flash (when in Master Serial / SPI configuration mode). 8.2.4 Steps for SPI Flash Sector Erase Operation 1.

  • Page 53: Steps For Spi Flash Read Operation

    2. Write the Page Program data to the ISP Space (PCI BAR 1) During the SPI Flash page program instruction, the bytes are transferred to the SPI Flash from lower to higher byte addresses. 3. Configure the SPI Flash Page Program instruction in the ISP Configuration Register (0xE4) The page base address and the page program instruction code must be set accordingly.

  • Page 54: Steps For Setting The Spi Flash Non-Volatile Qe Bit

    For reading the second SPI Flash page (base address 0x000100) write 0x00010003 to the ISP Configuration Register (0xE4). For reading the third SPI Flash page (base address 0x000200) write 0x00020003 to the ISP Configuration Register (0xE4). … For reading the last SPI Flash page (base address 0x3FFF00) write 0x00FF3F03 to the ISP Configuration Register (0xE4).

  • Page 55: Spi Flash Programming Via Jtag Header

    SPI Flash Programming via JTAG Header Programming the SPI Flash via the TPMC634 JTAG header requires the Xilinx iMPACT software and the Xilinx Platform Cable USB Programmer with the 2mm pitch 14 pos. flat ribbon cable. The Xilinx iMPACT software supports indirect SPI Flash programming by loading (and running) a special SPI core logic into the Spartan-6 FPGA that stimulates the FPGA I/O pins connected to the SPI Flash as required by the SPI programming protocol.
  • Page 56 • Generate the .MCS file TPMC634 User Manual Issue 1.0.1 Page 56 of 93...

  • Page 57: Spi Flash Programming

    8.3.2 SPI Flash Programming • Prepare a system and an appropriate PMC carrier • Connect the Xilinx Platform Cable USB Programmer USB port to the PC/Notebook Check: The status LED on the Xilinx Platform Cable USB Programmer should be lit orange •...
  • Page 58 • Verify the auto-detected JTAG chain (see figure below) and set the XC6SLX25 FPGA device to BYPASS • Assign the prepared .MCS file to the SPI Flash Right-Click on the SPI Flash and select Add SPI/BPI Flash TPMC634 User Manual Issue 1.0.1 Page 58 of 93...
  • Page 59 • Configure the SPI Flash Device Select the W25Q32BV as SPI PROM Data Width depends on the chosen SPI_buswidth BitGen option during the Xilinx ISE Design Flow • Program the SPI Flash Right-Click on the SPI Flash and select Program Select the Verify and Design-Specific Erase Before Programming check options TPMC634 User Manual Issue 1.0.1 Page 59 of 93...
  • Page 60 • Start SPI Flash programming TPMC634 User Manual Issue 1.0.1 Page 60 of 93...
  • Page 61 • Wait and Check successful SPI Flash programming • Turn the system off and unplug the Xilinx Platform Cable USB I/II JTAG port from the TPMC634 • Turn the system on again Check: The three TPMC634 LEDs must be lit green now (PG: Power Good, XO: MachXO2 Operating, S6: User FPGA Configured) TPMC634 User Manual Issue 1.0.1 Page 61 of 93...

  • Page 62: Local Bus Interface

    9 Local Bus Interface Local Bus Interface Notes The TPMC634 provides an on-board off-chip local bus for accessing the User FPGA as a target. For each optional user space (PCI BARs 2 to 5) there is a dedicated user space select signal. The TPMC634 local bus is synchronous and address/data multiplexed.

  • Page 63: Local Bus Master Abort (Local Bus Time-Out)

    9.2.1 Local Bus Master Abort (Local Bus Time-Out) The TPMC634 provides a local bus time-out monitor. The local bus time-out function is enabled by default and could be disabled in the Local Bus Interface Register. When the local bus time-out function is enabled, an internal timer is started at the beginning of a local bus cycle.

  • Page 64: Local Bus Signal Description

    Local Bus Signal Description Local Bus Signal Description Signal Direction Description Input for Local Bus Clock LB_CLK M & T A buffered version of the PCI clock signal (max. 33 MHz) Local Bus Reset 0: Reset State 1: Operating State Local Bus Reset sources are: M ...
  • Page 65 Local Bus Signal Description Signal Direction Description Byte Lane 0 <> AD[7:0] Byte Lane 1 <> AD[15:8] Byte Lane 2 <> AD[23:16] Byte Lane 3 <> AD[31:24] Local Bus Data / Address Phase Only valid during an active local bus cycle M ...

  • Page 66: Local Bus Interface Timing

    Local Bus Signal Description Signal Direction Description cycle by driving this signal low for one local clock cycle. In case of a target error indication during a local bus cycle, the master will terminate and discard the local bus cycle. Local Bus Target Interrupt The target may assert a level sensitive interrupt by driving M ...

  • Page 67: Local Bus Signal Protocol Example Diagrams

    Local Bus Signal Protocol Example Diagrams The following figures are showing some examples for the local bus signal protocol. LB_CLK LB_CYC# LB_SEL# LB_R/W# LB_D/A# LB_AD[] ADDR W_DAT ADDR R_DAT LB_MRDY# LB_TRDY# Fast Master Slow Target Local Bus Example LB_CLK LB_CYC# LB_SEL# LB_R/W# LB_D/A#...

  • Page 68: Figure 9-1 : Local Bus Signal Protocol Example Diagrams

    LB_CLK LB_CYC# LB_SEL# LB_R/W# LB_D/A# LB_AD[] ADDR W_DAT ADDR R_DAT LB_MRDY# LB_TRDY# Slow Master Fast Target Local Bus Example Figure 9-1 : Local Bus Signal Protocol Example Diagrams (1) Note that the following signals are only valid during an active local bus cycle: LB_R/W#, LB_D/A#, LB_MRDY#, LB_TRDY#, LB_MABT#, LB_TERR# (2) Note that (though shown in all examples above) the master may not necessarily be ready with a valid address in the very first clock cycle of the local bus cycle.

  • Page 69: Interrupts

    10 Interrupts 10.1 Interrupt Sources On the TPMC634 there are multiple interrupt sources capable of generating a PCI INTA# interrupt. The TPMC634 provides the following interrupt sources: • SPI Flash In-System Programming Interrupts There are two interrupts sources available for SPI Flash In-System Programming. One interrupt is for indicating that the SPI page data (PCI BAR 1) processing is done (so page read data may be read or next page write data may be written).

  • Page 70: Local Bus User Interrupt

    ISP SPI Page Data Done Interrupt If enabled, this event based interrupt becomes active when the ISP SPI Data Busy status bit changes from busy to not-busy. ISP Interrupt Clearing Interrupt clearing depends on the configured interrupt acknowledge mode. For Clear-by-Write mode, the interrupts are cleared by writing a ‘1’ to the corresponding interrupt status register bit(s).

  • Page 71: Leds

    11 LEDs The TPMC634 provides three green LEDs on the cards back side. LED Description Description Label ON: +1.2V and +3.3V on-Board Power Supplies Power Good are indicating Power Good Status Status LED OFF: +1.2V and/or +3.3V on-Board Power Supplies are not indicating Power Good Status This LED is SW controlled by a bit in the Control MachXO2 FPGA &...

  • Page 72: Jtag Header

    12 JTAG Header The TPMC634 provides a 14 pos., dual-row, 2mm pitch, right-angle JTAG header (near the 68 pos. front I/O connector) for accessing the Spartan-6 User FPGA JTAG port. The header mechanics and pin assignment support the direct connection of the Xilinx Platform Cable USB programmer 14 pos. 2mm flat ribbon cable. The TPMC634 JTAG Header is intended to be used with the Xilinx iMPACT software and the Xilinx Platform Cable USB Programmer.

  • Page 73: Figure 12-1: Jtag Header Location

    Figure 12-2: JTAG Header Location TPMC634 User Manual Issue 1.0.1 Page 73 of 93...

  • Page 74: Board Hw-Configuration

    13 Board HW-Configuration 13.1 Readable DIP-Switch The TPMC634 provides a readable 4 position DIP-Switch. The DIP-switch has no functional side-effects. The current DIP-Switch setting is readable in the DIP-Switch Register (Offset 0xF0) in the PCI Target Register Space (PCI BAR0) and may be used for identifying a certain TPMC634 card in a system.

  • Page 75: O Interface

    14 I/O Interface The TPMC634 I/O interface signals are available on both the 68 pin front-I/O connector and the 64 pin P14 rear-I/O connector. Only one TPMC634 I/O interface must be used / installed at a time, either the front-I/O interface or the rear-I/O interface! Do not use / install both the front I/O interface and the rear I/O interface at the same time! 14.1...

  • Page 76: Figure 14-1: Single-Ended I/O Line Interface

    Pull Resistor Reference: 3,3V | 5V | GND | Open FPGA_OE[i] XILINX 74LVT126 FPGA FPGA_OUT[i] TTL I/O Line X1 / P14 ESD Protection 3.3V FPGA_IN[i] 74LVT126 Figure 14-1: Single-Ended I/O Line Interface 14.1.1.1 Output Level & Output Current Because of the 47 ohm series resistor, there is a reduced high-level voltage at the I/O pin when the output buffer sources a noticeable current to the external load while driving a high-level.

  • Page 77: Differential I/O Line Interface

    14.1.2 Differential I/O Line Interface For differential I/O lines (TPMC634-11R/-12R/-13R/-14R) the on-board line transceiver type depends on the product variant. On the TPMC634-11R and TPMC634-12R MAX3078E (or compatible) ESD protected RS485/RS422 transceivers are used as differential line transceivers. On the TPMC634-13R and TPMC634-14R SN65MLVD206 (or compatible) M-LVDS Type 2 transceivers are used as differential line transceivers.

  • Page 78: I/O Connectors

    14.2 I/O Connectors 14.2.1 Front-I/O Connector Part Number Pin-Count Connector Type HD68 SCSI3 Source & Order Info Tyco 787082-7 or compatible Table 14-1 : Front I/O Connector Part Number Figure 14-3: Front Panel I/O Connector Numbering 14.2.2 Rear-I/O Connector Part Number Pin-Count Connector Type Mezzanine IEEE 1386 Plug...

  • Page 79: Front-I/O Pin Assignment

    14.4 Front-I/O Pin Assignment TPMC634 Order Option TPMC634 Order Option -x1 & -x3 -x2 & -x4 -x1 & -x3 -x2 & -x4 IO_0A/- IO_0A/- IO_0B/+ IO_0B/+ IO_0 IO_1 IO_1A/- IO_1A/- IO_1B/+ IO_1B/+ IO_2 IO_3 IO_2A/- IO_2A/- IO_2B/+ IO_2B/+ IO_4 IO_5 IO_6 IO_3A/- IO_3A/-...

  • Page 80: Rear-I/O Pin Assignment

    14.5 Rear-I/O Pin Assignment TPMC634 Order Option TPMC634 Order Option -x1 & -x3 -x2 & -x4 -x1 & -x3 -x2 & -x4 IO_0A/- IO_0A/- IO_0B/+ IO_0B/+ IO_0 IO_1 IO_1A/- IO_1A/- IO_1B/+ IO_1B/+ IO_2 IO_3 IO_2A/- IO_2A/- IO_2B/+ IO_2B/+ IO_4 IO_5 IO_6 IO_3A/- IO_3A/-...

  • Page 81: Appendix A: User Fpga Port Map

    15 Appendix A: User FPGA Port Map The following may be used as the VHDL top level entity port map for the user FPGA application project. entity tpmc634_xc6slx25_exa is port( -- Local Bus Interface Signals LB_RST_n : in std_logic; -- Reset LB_CLK : in std_logic;...

  • Page 82: Appendix B: User Fpga Constraint File

    16 Appendix B: User FPGA Constraint File The following may be used as the Xilinx ISE design flow user constraint file (UCF) for the user FPGA application project. ############################################################################### # User Constraints File for TPMC634 User FPGA Example ############################################################################### # Project: TPMC634 User FPGA Example # Device: XC6SLX25-2FGG484I...
  • Page 83 NET "LB_AD<7>" LOC = AB9; NET "LB_AD<8>" LOC = W10; NET "LB_AD<9>" LOC = Y10; NET "LB_AD<10>" LOC = AA8; NET "LB_AD<11>" LOC = AB8; NET "LB_AD<12>" LOC = W8; NET "LB_AD<13>" LOC = V7; NET "LB_AD<14>" LOC = W9; NET "LB_AD<15>"...
  • Page 84 NET "IO_IN<14>" LOC = E3 | PULLDOWN; NET "IO_IN<15>" LOC = D1 | PULLDOWN; NET "IO_IN<16>" LOC = G6 | PULLDOWN; NET "IO_IN<17>" LOC = H8 | PULLDOWN; NET "IO_IN<18>" LOC = A2 | PULLDOWN; NET "IO_IN<19>" LOC = J1 | PULLDOWN; NET "IO_IN<20>"...
  • Page 85 NET "IO_OUT<7>" LOC = M2; NET "IO_OUT<8>" LOC = L1; NET "IO_OUT<9>" LOC = K6; NET "IO_OUT<10>" LOC = H3; NET "IO_OUT<11>" LOC = G3; NET "IO_OUT<12>" LOC = H5; NET "IO_OUT<13>" LOC = G4; NET "IO_OUT<14>" LOC = E1; NET "IO_OUT<15>"...
  • Page 86 NET "IO_OE<0>" LOC = W3; NET "IO_OE<1>" LOC = T3; NET "IO_OE<2>" LOC = M5; NET "IO_OE<3>" LOC = V1; NET "IO_OE<4>" LOC = T2; NET "IO_OE<5>" LOC = R1; NET "IO_OE<6>" LOC = N3; NET "IO_OE<7>" LOC = M1; NET "IO_OE<8>"...
  • Page 87 NET "IO_OE<58>" LOC = L17; NET "IO_OE<59>" LOC = H21; NET "IO_OE<60>" LOC = L19; NET "IO_OE<61>" LOC = J22; NET "IO_OE<62>" LOC = W14; NET "IO_OE<63>" LOC = AB15; # Miscellaneous & Reserved CONFIG PROHIBIT = AA2; # LB_REQ_n CONFIG PROHIBIT = AB2;...
  • Page 88 TIMEGRP "LOCAL_BUS_CTRL_OUTPUTS" OFFSET = OUT 12 ns AFTER "LB_CLK" RISING; # NET "LB_RST_n" TIG; # Auxiliary Clock (33.25 MHz) NET "AUX_CLK" TNM_NET = "AUX_CLK"; TIMESPEC "TS_2" = PERIOD "AUX_CLK" 30 ns HIGH 40%; # Baud Rate Clock (7.3728 MHz) NET "BAUD_CLK" TNM_NET = "BAUD_CLK"; TIMESPEC "TS_3"...

  • Page 89: Appendix C: Pre-Installed User Fpga Example Application

    17 Appendix C: Pre-Installed User FPGA Example Application The TPMC634 Re-Configurable FPGA card comes with a pre-installed User FPGA Example application stored in the on-board SPI Flash. After power-up the TPMC634 User FPGA automatically loads the FPGA configuration from the on-board SPI Flash and runs the TPMC634 User FPGA Example application.

  • Page 90: User Fpga Example Register Description

    0xDC Test 0xE0 Clock Counter Control Register 0xE4 Clock Counter Register – Local Bus Clock 0xE8 Clock Counter Register – Auxiliary Clock 0xEC Clock Counter Register – Baud Rate Clock 0xF0 Reserved 0xF4 Reserved 0xF8 General R/W Register 0xFC Version Register Table 17-1 : User FPGA Example Register Map 17.2 User FPGA Example Register Description...

  • Page 91: Pmc I/O Output Register (Upper) (0X0C)

    Table 17-4: PMC I/O Output Register (Lower) (0x08) 17.2.4 PMC I/O Output Register (Upper) (0x0C) Reset Symbol Description Access Value PMC I/O Line [63:32] Output Register 0: Set PMC I/O Line Output State Low 31:0 IO_OUT all 0 1: Set PMC I/O Line Output State High Note that for driving the configured output level, the corresponding line output must also be enabled.

  • Page 92: Pmc I/O Falling Edge Interrupt Enable Register (0X24)

    17.2.8 PMC I/O Falling Edge Interrupt Enable Register (0x24) Reset Symbol Description Access Value Falling Edge Interrupt Enable for PMC I/O Line [31:0] Inputs IO_F_ 31:0 all 0 0: Disable PMC I/O Line Falling Edge Interrupt INT_EN 1: Enable PMC I/O Line Falling Edge Interrupt Table 17-9: PMC I/O Falling Edge Interrupt Enable Register (0x24) 17.2.9 PMC I/O Interrupt Status Register (0x28) Reset...

  • Page 93: Clock Counter Register - Local Bus Clock (0Xe4)

    17.2.11 Clock Counter Register – Local Bus Clock (0xE4) Reset Symbol Description Access Value Local Bus Clock Counter Register Register for counting Local Bus Clock cycles. 31:0 all 0 CCR_LB The Local Bus Clock frequency matches the PMC PCI clock frequency (typically 33MHz). Table 17-12: Clock Counter Register –...

This manual is also suitable for:

Tpmc634-10rTpmc634-11rTpmc634-12rTpmc634-13rTpmc634-14r

Table of Contents