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Tews Technologies TPMC533 User Manual

32x adc, 16x/0x dac and 8x digital i/o
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The Embedded I/O Company
TPMC533
32x ADC, 16x/0x DAC and 8x Digital I/O
Version 1.0
User Manual
Issue 1.0.1
May 2018
TEWS TECHNOLOGIES GmbH
Am Bahnhof 7
25469 Halstenbek, Germany
Phone: +49 (0) 4101 4058 0
Fax: +49 (0) 4101 4058 19
e-mail:
info@tews.com
www.tews.com

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  • Page 1 TPMC533 32x ADC, 16x/0x DAC and 8x Digital I/O Version 1.0 User Manual Issue 1.0.1 May 2018 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek, Germany Phone: +49 (0) 4101 4058 0 Fax: +49 (0) 4101 4058 19 e-mail: info@tews.com...
  • Page 2 (RoHS compliant) reserves the right to change the product described in this document at any time without notice. TPMC533-20R TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or use of the Channels Simultaneous Sampling device described herein.
  • Page 3 Issue Description Date 1.0.0 Initial issue December 2017 1.0.1 Power Requirements revised May 2018 TPMC533 User Manual Issue 1.0.1 Page 3 of 107...

  • Page 4: Table Of Contents

    10 PIN ASSIGNMENT – I/O CONNECTOR ..............104 10.1 Front I/O ............................104 10.2 P14 Back I/O ..........................105 11 TA114 CABLE......................106 11.1 X2 Connector ..........................106 11.2 X3 Connector ..........................107 TPMC533 User Manual Issue 1.0.1 Page 4 of 107...
  • Page 5 TABLE 3-21: ADC SEQUENCER CONTROL REGISTER ................27 TABLE 3-22: ADC SEQUENCER STATUS REGISTER ................. 29 TABLE 3-23: NUMBER OF CONVERSIONS REGISTER ................30 TABLE 3-24: CONVERSION COUNT REGISTER ..................30 TPMC533 User Manual Issue 1.0.1 Page 5 of 107...
  • Page 6 TABLE 3-64: DIO RISING EDGE INTERRUPT ENABLE REGISTER ............66 TABLE 3-65: DIO FALLING EDGE INTERRUPT ENABLE REGISTER ............67 TABLE 3-66: INTERRUPT STATUS REGISTER.................... 68 TABLE 3-67: ERROR INTERRUPT STATUS REGISTER ................69 TPMC533 User Manual Issue 1.0.1 Page 6 of 107...
  • Page 7 TABLE 10-1: PIN ASSIGNMENT FRONT I/O ....................104 TABLE 10-2: PIN ASSIGNMENT P14 BACK I/O ..................105 TABLE 11-1 : TA114 X2 CONNECTOR ......................106 TABLE 11-2 : TA114 X3 CONNECTOR ......................107 TPMC533 User Manual Issue 1.0.1 Page 7 of 107...

  • Page 8: Product Description

    P14 or Front I/O, created by another module. A Frame Trigger signal, which can also either be generated by the TPMC533 and output on P14/Front I/O or generated by other modules and input from P14/Front I/O, can be used to synchronize ADC frames and DAC frames.

  • Page 9: Figure 1-1 : Block Diagram

    Figure 1-1 : Block Diagram TPMC533 User Manual Issue 1.0.1 Page 9 of 107...

  • Page 10: Technical Specification

    Driver Level LVTTL (3.3V) Receiver 5V tolerant Source Current 15mA Sink Current I/O Connectors Front I/O 100-pin HDRA (Honda HDRA-EC100LFDT-SL+ or compatible) P14 Back I/O 64-pin Mezzanine Connector (Molex 71436-2864 or compatible) TPMC533 User Manual Issue 1.0.1 Page 10 of 107...

  • Page 11: Table 2-1 : Technical Specification

    If FIT rates are not available, MIL-HDBK-217F and MIL-HDBK-217F Notice 2 formulas are used for FIT rate calculation. Humidity 5 – 95 % non-condensing Weight TPMC533-10R: 72.8g TPMC533-20R: 72.5g Table 2-1 : Technical Specification TPMC533 User Manual Issue 1.0.1 Page 11 of 107...

  • Page 12: Pci Interface

    Table 3-1 : PCI Identifier PCI Base Address Register Configuration The two address spaces on the TPMC533 are accessed from the PCI side by addressing two PCI Base Address Registers mapped in the PCI Memory Space. PCI Base Address Register...

  • Page 13: Register Space

    0x074 ADC2 Correction Register G 0x078 ADC2 Correction Register H 0x07C ADC2 Data Register A & B 0x080 ADC2 Data Register C & D 0x084 ADC2 Data Register E & F TPMC533 User Manual Issue 1.0.1 Page 13 of 107...
  • Page 14 ADC4 Data Register A & B 0x108 ADC4 Data Register C & D 0x10C ADC4 Data Register E & F 0x110 ADC4 Data Register G & H 0x114 ADC4 Mode Register 0x118 Reserved 0x11C Reserved TPMC533 User Manual Issue 1.0.1 Page 14 of 107...
  • Page 15 DAC2 Configuration Register 0x19C Reserved 0x1A0 DAC2 Correction Register A 0x1A4 DAC2 Correction Register B 0x1A8 DAC2 Correction Register C 0x1AC DAC2 Correction Register D 0x1B0 DAC2 Data Register A & B TPMC533 User Manual Issue 1.0.1 Page 15 of 107...
  • Page 16 DAC Sequencer Control Register 0x2EC DAC Sequencer Status Register 0x2F0 Reserved 0x2F4 Number of Conversions Register 0x2F8 Conversion Count Register 0x2FC FIFO Level Register 0x300 Reserved 0x304 Reserved 0x308 DMA Buffer Base Address Register TPMC533 User Manual Issue 1.0.1 Page 16 of 107...
  • Page 17 DIO Rising Edge Interrupt Enable Register 0x378 DIO Falling Edge Interrupt Enable Register 0x37C Reserved 0x380 Reserved 0x384 Interrupt Status Register 0x388 Error Interrupt Status Register 0x38C DIO Interrupt Status Register 0x390 Reserved 0x394 Reserved TPMC533 User Manual Issue 1.0.1 Page 17 of 107...

  • Page 18: Table 3-3 : Register Space

    Temperature Sensor Data Register 0x3B0 to 0x3F8 Reserved 0x3FC Firmware Version Register Table 3-3 : Register Space For the TPMC533-20R the DAC Global Registers, DAC Device Registers and DAC Sequencer Registers are reserved. TPMC533 User Manual Issue 1.0.1 Page 18 of 107...

  • Page 19: Table 3-4 : Register Bit Access Types

    When reading reserved register bits, the value is undefined. Reserved register bits shall be written as '0'. 3.2.1.1 ADC Global Registers The following registers exist only once and deal with all ADCs on-board the TPMC533. 3.2.1.1.1 Global ADC Control Register (0x000) The Global ADC Control Register provides control options for each ADC (for all eight ADC Channels of each ADC) on-board the TPMC533.

  • Page 20: Table 3-6 : Global Adc Status Register

    3.2.1.1.2 Global ADC Status Register (0x004) For each ADC (for all eight ADC Channels of each ADC) on-board the TPMC533, status information can be read from this read-only register. Reset Symbol Description Access Value 31:4 Reserved ADC4 Busy ADC4_BUSY Refer to the ADC1 Busy bit for description.

  • Page 21: Table 3-7 : Adc Configuration Register

    Channel± pins. Also see chapter “ADC Data Coding”. Input Voltage Range ADCx_IR ±5V ±10V Allow a settling time of about 100µs when the ADC input range is changed. Table 3-7 : ADC Configuration Register TPMC533 User Manual Issue 1.0.1 Page 21 of 107...

  • Page 22: Table 3-8 : Adc Correction Register A

    Table 3-11: ADC Correction Register D Reset Symbol Description Access Value 31:16 ADCx_GAIN_E Gain Correction Value ADC Channel E 0x0000 15:0 ADCx_OFFSET_E Offset Correction Value ADC Channel E 0x0000 Table 3-12: ADC Correction Register E TPMC533 User Manual Issue 1.0.1 Page 22 of 107...

  • Page 23: Table 3-13: Adc Correction Register F

    Table 3-14: ADC Correction Register G Reset Symbol Description Access Value 31:16 ADCx_GAIN_H Gain Correction Value ADC Channel H 0x0000 15:0 ADCx_OFFSET_H Offset Correction Value ADC Channel H 0x0000 Table 3-15: ADC Correction Register H TPMC533 User Manual Issue 1.0.1 Page 23 of 107...

  • Page 24: Table 3-16: Adc Data Register A & B

    Table 3-18: ADC Data Register E & F Reset Symbol Description Access Value 31:16 ADCx_DATA_H ADC Data ADC Channel H 0x0000 15:0 ADCx_DATA_G ADC Data ADC Channel G 0x0000 Table 3-19: ADC Data Register G & H TPMC533 User Manual Issue 1.0.1 Page 24 of 107...

  • Page 25: Table 3-20: Adc Mode Register

    In Sequencer Mode, analog inputs are sampling periodically at a configurable conversion rate. Table 3-20: ADC Mode Register Note that all eight channels of an ADC are always operating in the same Operating Mode. TPMC533 User Manual Issue 1.0.1 Page 25 of 107...
  • Page 26 DMA Controller can be disabled. The DMA Controller is reset when disabled. 15:9 Reserved FIFO Clear When set to 1, the ADC Sequencer's internal FIFO is ADC_SEQ_FIFO_CLR cleared. This bit is self-clearing TPMC533 User Manual Issue 1.0.1 Page 26 of 107...

  • Page 27: Table 3-21: Adc Sequencer Control Register

    Error. In this case the ADC Sequencer Status Register must be read and the Input Unit can be disabled. The Input Unit is reset when disabled. Table 3-21: ADC Sequencer Control Register TPMC533 User Manual Issue 1.0.1 Page 27 of 107...
  • Page 28 Indicates that the DMA Controller is currently in Idle State. WR_DMA_IDLE A DMA transfer may be started (a DMA buffer may be provided) by writing to the DMA Buffer Length Register. TPMC533 User Manual Issue 1.0.1 Page 28 of 107...

  • Page 29: Table 3-22: Adc Sequencer Status Register

    This bit is cleared when the configured Number of Conversions has been performed (for a single frame). Reserved Input Unit Idle IU_IDLE Indicates that the Input Unit is currently in Idle State. Table 3-22: ADC Sequencer Status Register TPMC533 User Manual Issue 1.0.1 Page 29 of 107...

  • Page 30: Table 3-23: Number Of Conversions Register

    Control Register. 0000 Frame Mode: The value is automatically reset at a Frame Trigger event (except for the case when an Input Unit Frame Error occurred). Table 3-24: Conversion Count Register TPMC533 User Manual Issue 1.0.1 Page 30 of 107...

  • Page 31: Table 3-25: Fifo Level Register

    Host RAM the next ADC Data is written to. It can be used 0000 to determine how much space is left in the provided DMA Buffer. Table 3-28: DMA Buffer Next Address Register TPMC533 User Manual Issue 1.0.1 Page 31 of 107...

  • Page 32: Table 3-29: Dma Status Base Address Register

    0000 enabled) as soon as the processing of a DMA Buffer is done. Table 3-29: DMA Status Base Address Register Like the registers of the TPMC533, the DMA Status must be interpreted Little Endian. Symbol Description Reserved DMA Buffer Termination Status...

  • Page 33: Table 3-31: Global Dac Control Register

    3.2.1.4 DAC Global Registers The following registers exist only once and deal with all DACs on-board the TPMC533. These Registers are Reserved on TPMC533-20R. 3.2.1.4.1 Global DAC Control Register (0x158) The Global DAC Control Register provides control options for each DAC (for all four DAC Channels of each DAC) on-board the TPMC533.

  • Page 34: Table 3-32: Global Dac Status Register

    3.2.1.4.2 Global DAC Status Register (0x15C) For each DAC (for all four DAC Channels of each DAC) on-board the TPMC533, status information can be read from this read-only register. Reset Symbol Description Access Value 31:12 Reserved DAC4 Settle DAC4_SETTLE Refer to the DAC1 Settle bit for description.
  • Page 35 3.2.1.5 DAC Device Registers The following registers exist multiple times and each of the registers deals with a single DAC (four DAC Channels) on-board the TPMC533. These Registers are Reserved on TPMC533-20R. 3.2.1.5.1 DAC Configuration Registers (0x168, 0x198, 0x1C8 and 0x1F8) There is a dedicated DAC Configuration Register for each DAC (for all four DAC Channels of each DAC).
  • Page 36 DAC Channel B Output Range Also see chapter “DAC Data Coding”. OR_B Output Voltage Range +5V (unipolar) +10V (unipolar) +10.8V (unipolar) 10:8 DACx_OR_B ±5V (bipolar) ±10V (bipolar) ±10.8V (bipolar) Reserved Reserved TPMC533 User Manual Issue 1.0.1 Page 36 of 107...

  • Page 37: Table 3-33: Dac Configuration Register

    DAC Channel A Output Range Also see chapter “DAC Data Coding”. OR_A Output Voltage Range +5V (unipolar) +10V (unipolar) +10.8V (unipolar) DACx_OR_A ±5V (bipolar) ±10V (bipolar) ±10.8V (bipolar) Reserved Reserved Table 3-33: DAC Configuration Register TPMC533 User Manual Issue 1.0.1 Page 37 of 107...

  • Page 38: Table 3-34: Dac Correction Register A

    Table 3-36: DAC Correction Register C Reset Symbol Description Access Value 31:16 DACx_GAIN_D Gain Correction Value DAC Channel D 0x0000 15:0 DACx_OFFSET_D Offset Correction Value DAC Channel D 0x0000 Table 3-37: DAC Correction Register D TPMC533 User Manual Issue 1.0.1 Page 38 of 107...

  • Page 39: Table 3-38: Dac Data Register A & B

    Table 3-38: DAC Data Register A & B Reset Symbol Description Access Value 31:16 DACx_DATA_D DAC Data DAC Channel D 0x0000 15:0 DACx_DATA_C DAC Data DAC Channel C 0x0000 Table 3-39: DAC Data Register C & D TPMC533 User Manual Issue 1.0.1 Page 39 of 107...

  • Page 40: Table 3-40: Dac Status Register

    ‘1’ when powered up. DACx_PUA On detection of an over-current or thermal overtemperature condition, DAC channel A will power down automatically. DACx_PUA will be cleared to reflect this. Table 3-40: DAC Status Register TPMC533 User Manual Issue 1.0.1 Page 40 of 107...

  • Page 41: Table 3-41: Dac Mode Register

    In Sequencer Mode, the analog outputs are updated simultaneously and periodically at a configurable conversion rate. Table 3-41: DAC Mode Register Note that all four channels of a DAC are always operating in the same Operating Mode. TPMC533 User Manual Issue 1.0.1 Page 41 of 107...
  • Page 42 Frame Mode is used for repetitive blocks of digital-to-analog conversions triggered by a Frame Trigger at a configurable Frame Trigger Rate. These Registers are Reserved on TPMC533-20R. 3.2.1.6.1 DAC Sequencer Control Register (0x2E8)
  • Page 43 In Frame Mode, the configured Number of Conversions is performed starting with the next Conversion Clock after a Frame Trigger occurred. Output Unit Reset OU_RESET Writing '1' to this bit resets the Output Unit. This bit is self-clearing TPMC533 User Manual Issue 1.0.1 Page 43 of 107...

  • Page 44: Table 3-42: Dac Sequencer Control Register

    Unit Error. In this case the DAC Sequencer Status Register must be read and the Output Unit can be disabled. The Output Unit is reset when disabled. Table 3-42: DAC Sequencer Control Register TPMC533 User Manual Issue 1.0.1 Page 44 of 107...
  • Page 45 In case of this error, the conversion process is terminated (no more conversion pulses are generated) and the Output Unit operation is stopped. This bit is automatically cleared when the Output Unit is disabled. TPMC533 User Manual Issue 1.0.1 Page 45 of 107...

  • Page 46: Table 3-43: Dac Sequencer Status Register

    Sequencer Mode are updated simultaneously. After each sequencer controlled conversion, the DACs are pre-loaded with DAC Data for the next conversion (if data is available in the DAC Sequencer's internal FIFO). TPMC533 User Manual Issue 1.0.1 Page 46 of 107...

  • Page 47: Table 3-45: Conversion Count Register

    A write to the DMA Buffer Length Register initiates the 0x0000 27:0 RD_DMA_BUF_LEN DMA transfer. 0000 The Initiation of DMA transfers is only possible if RD_DMA_IDLE in the DAC Sequencer Status Register is ‘1’. Table 3-48: DMA Buffer Length Register TPMC533 User Manual Issue 1.0.1 Page 47 of 107...

  • Page 48: Table 3-49: Dma Buffer Next Address Register

    Host RAM the next DAC Data is read from. It can be used 0000 to determine how much information is left in the provided DMA Buffer. Table 3-49: DMA Buffer Next Address Register TPMC533 User Manual Issue 1.0.1 Page 48 of 107...

  • Page 49: Table 3-50: Conversion Clock 1 Generator Register

    These bits set the divider for the selected Internal Clock FFFF Source. Table 3-50: Conversion Clock 1 Generator Register CLK1_GEN_SRC CLK1_GEN_DIV+1 The frequency of the Conversion Clock 1 Generator output is: TPMC533 User Manual Issue 1.0.1 Page 49 of 107...

  • Page 50: Table 3-51: Conversion Clock 2 Generator Register

    These bits set the divider for the selected Internal Clock FFFF Source. Table 3-51: Conversion Clock 2 Generator Register CLK2_GEN_SRC CLK2_GEN_DIV+1 The frequency of the Conversion Clock 2 Generator output is: TPMC533 User Manual Issue 1.0.1 Page 50 of 107...

  • Page 51: Table 3-52: Frame Trigger Generator Register 1

    Sets the number of Frame Triggers to be generated. 27:0 FRAME_TRIG_GEN_NUM 0000 If set to '0', Frame Triggers are generated continuously at the configured Frame Trigger frequency. Table 3-53: Frame Trigger Generator Register 2 TPMC533 User Manual Issue 1.0.1 Page 51 of 107...

  • Page 52: Table 3-54: Conversion Signals Generator Enable Register

    Conversion Clock 1 Generation Enable 0: Conversion Clock 1 Generation Disabled CLK1_GEN_ENA 1: Conversion Clock 1 Generation Enabled If disabled, the clock output is ‘1’. Table 3-54: Conversion Signals Generator Enable Register TPMC533 User Manual Issue 1.0.1 Page 52 of 107...

  • Page 53: Table 3-55: Conversion Signals Generator Output Driver Register

    The regular DIO output operation dominates, thus if a bit is set in the DIO Output Enable Register, the corresponding value set in the DIO Output Register is driven out on the DIO Front I/O pin (regardless of the Conversion Signals Generator Output Driver Register setting). TPMC533 User Manual Issue 1.0.1 Page 53 of 107...

  • Page 54: Table 3-56: Conversion Signals Source Selection Register

    Output Driver disabled Conversion Signal Generators Multiboard Master Card P14 Back I/O or Front I/O P14 Back I/O or Front I/O Multiboard Target Card Output Driver disabled P14 Back I/O or Front I/O TPMC533 User Manual Issue 1.0.1 Page 54 of 107...

  • Page 55: Table 3-57: Frame Timer Register

    Trigger occurs. Reserved Frame Timer Value 0xFFF 27:0 FRAME_TIMER_VAL The Frame Timer expires after FRAME_TIMER_VAL + 1 FFFF clock cycles of the selected Frame Timer Clock Source. Table 3-57: Frame Timer Register TPMC533 User Manual Issue 1.0.1 Page 55 of 107...

  • Page 56: Table 3-58: Dio Input Register

    3.2.1.8 DIO Registers The following registers deal with the Digital I/O interface on the Front I/O connector of the TPMC533. 3.2.1.8.1 DIO Input Register (0x354) The Digital I/O receivers are always enabled, so each DIO level can always be monitored.

  • Page 57: Table 3-59: Dio Input Filter Debounce Register

    After an input pin performs a rising or a falling edge, T PASS defines how long this new logic level must be stable before the level change is passed on to the internal logic. Table 3-59: DIO Input Filter Debounce Register TPMC533 User Manual Issue 1.0.1 Page 57 of 107...

  • Page 58: Table 3-60: Dio Output Register

    DIO Direction Register writes to this bit will take OUT1 no effect 0: Digital I/O 1 is driven logic low. 1: Digital I/O 1 is driven logic high. Table 3-60: DIO Output Register TPMC533 User Manual Issue 1.0.1 Page 58 of 107...

  • Page 59: Table 3-61: Dio Output Enable Register

    Refer to the DIO1 Output Enable bit for description. DIO1 Output Enable 0: Digital I/O 1 output transmitter is disabled. 1: Digital I/O 1 output transmitter is enabled. Table 3-61: DIO Output Enable Register TPMC533 User Manual Issue 1.0.1 Page 59 of 107...
  • Page 60 If enabled, in Manual Mode an interrupt will be generated after a conversion of ADC1 is finished and ADC Data is available (ADC1_BUSY changes from '1' to '0' in Global ADC Status Register). TPMC533 User Manual Issue 1.0.1 Page 60 of 107...
  • Page 61 1: enabled DAC1_DONE_ENA If enabled, in Manual Mode an interrupt will be generated after DAC1 has settled (DAC1_SETTLE changes from '1' to '0' in Global DAC Status Register). For TPMC533-20R: Reserved TPMC533 User Manual Issue 1.0.1 Page 61 of 107...

  • Page 62: Table 3-62: Interrupt Enable Register

    0: disabled 1: enabled RD_DMA_TERM_IRQ_ENA If enabled, an interrupt is asserted when the DMA Controller of the DAC Sequencer terminates its provided DMA Buffer. For TPMC533-20R: Reserved Table 3-62: Interrupt Enable Register TPMC533 User Manual Issue 1.0.1 Page 62 of 107...
  • Page 63 Enable IRQ at ADC Sequencer DMA Error 0: disabled 1: enabled WR_DMA_ERR_IRQ_ENA If enabled, an interrupt is asserted when the DMA Controller of the ADC Sequencer faces a PCI Bus Abort. TPMC533 User Manual Issue 1.0.1 Page 63 of 107...
  • Page 64 Enable IRQ at DAC Sequencer DMA Error 0: disabled 1: enabled RD_DMA_ERR_IRQ_ENA If enabled, an interrupt is asserted when the DMA Controller of the DAC Sequencer faces a PCI Bus Abort. For TPMC533-20R: Reserved TPMC533 User Manual Issue 1.0.1 Page 64 of 107...

  • Page 65: Table 3-63: Error Interrupt Enable Register

    If enabled, an interrupt is asserted when the DAC1 status is read and any of the over-current bits or the thermal shutdown bit is set. For TPMC533-20R: Reserved Table 3-63: Error Interrupt Enable Register TPMC533 User Manual Issue 1.0.1 Page 65 of 107...

  • Page 66: Table 3-64: Dio Rising Edge Interrupt Enable Register

    Enable IRQ at DIO 1 Rising Edge 0: disabled DIO1_RISE 1: enabled If enabled, an interrupt is asserted when a rising edge is detected at DIO1. Table 3-64: DIO Rising Edge Interrupt Enable Register TPMC533 User Manual Issue 1.0.1 Page 66 of 107...

  • Page 67: Table 3-65: Dio Falling Edge Interrupt Enable Register

    Enable IRQ at DIO 1 Falling Edge 0: disabled DIO1_FALL 1: enabled If enabled, an interrupt is asserted when a falling edge is detected at DIO1. Table 3-65: DIO Falling Edge Interrupt Enable Register TPMC533 User Manual Issue 1.0.1 Page 67 of 107...

  • Page 68: Table 3-66: Interrupt Status Register

    IRQ at ADC Sequencer DMA Buffer Termination Reserved IRQ at Output Unit Number of Conversions done OU_CONV_DONE_IRQ For TPMC533-20R: Reserved Reserved IRQ at DAC Sequencer DMA Buffer Termination RD_DMA_TERM_IRQ For TPMC533-20R: Reserved Table 3-66: Interrupt Status Register TPMC533 User Manual Issue 1.0.1 Page 68 of 107...

  • Page 69: Table 3-67: Error Interrupt Status Register

    For TPMC533-20R: Reserved IRQ at DAC3 Alert DAC3_ALERT For TPMC533-20R: Reserved IRQ at DAC2 Alert DAC2_ALERT For TPMC533-20R: Reserved IRQ at DAC1 Alert DAC1_ALERT For TPMC533-20R: Reserved Table 3-67: Error Interrupt Status Register TPMC533 User Manual Issue 1.0.1 Page 69 of 107...

  • Page 70: Table 3-68: Dio Interrupt Status Register

    Indicates a rising or/and falling edge at Digital I/O 1 DIO1 depending on the configuration in the DIO Rising Edge Interrupt Enable Register and the DIO Falling Edge Interrupt Enable Register Table 3-68: DIO Interrupt Status Register TPMC533 User Manual Issue 1.0.1 Page 70 of 107...

  • Page 71: Table 3-69: Global Configuration Register

    0: Little Endian Mode (16bit digital values are stored in Little DMA_ENDIAN_CONF Endian format in Host RAM) 1: Big Endian Mode (16bit digital values are stored in Big Endian format in Host RAM) Table 3-69: Global Configuration Register TPMC533 User Manual Issue 1.0.1 Page 71 of 107...

  • Page 72: Table 3-70: Dio Pull Resistor Register

    Pull-Ups to +5V Pull-Ups to +3.3V Pull-Downs to GND Table 3-71: P14 Back I/O Pull Resistor Register Note that the default configuration for the P14 Back I/O Pull Resistors is floating. TPMC533 User Manual Issue 1.0.1 Page 72 of 107...

  • Page 73: Table 3-72: Correction Data Eeprom Control/Status Register

    The EEBSY bit is set during this procedure. Before setting the EELOCK nibble to 0xABCD, software should check that the EEBSY bit is clear. Table 3-72: Correction Data EEPROM Control/Status Register TPMC533 User Manual Issue 1.0.1 Page 73 of 107...

  • Page 74: Table 3-73: Temperature Sensor Trigger Register

    Table 3-74: Temperature Sensor Data Register 3.2.1.10.7 Firmware Version Register (0x3FC) Reset Symbol Description Access Value Major & minor version, revision and build number of the 31:0 FPGA firmware. Table 3-75: Firmware Version Register TPMC533 User Manual Issue 1.0.1 Page 74 of 107...

  • Page 75: Correction Data Rom

    CORR 0x02A ADC2 Channel C Gain CORR 0x02C ADC2 Channel D Offset CORR 0x02E ADC2 Channel D Gain CORR 0x030 ADC2 Channel E Offset CORR 0x032 ADC2 Channel E Gain CORR TPMC533 User Manual Issue 1.0.1 Page 75 of 107...
  • Page 76 CORR 0x076 ADC4 Channel F Gain CORR 0x078 ADC4 Channel G Offset CORR 0x07A ADC4 Channel G Gain CORR 0x07C ADC4 Channel H Offset CORR 0x07E ADC4 Channel H Gain CORR TPMC533 User Manual Issue 1.0.1 Page 76 of 107...
  • Page 77 CORR 0x0C4 ADC3 Channel B Offset CORR 0x0C6 ADC3 Channel B Gain CORR 0x0C8 ADC3 Channel C Offset CORR 0x0CA ADC3 Channel C Gain CORR 0x0CC ADC3 Channel D Offset CORR TPMC533 User Manual Issue 1.0.1 Page 77 of 107...
  • Page 78 CORR 0x0F6 ADC4 Channel F Gain CORR 0x0F8 ADC4 Channel G Offset CORR 0x0FA ADC4 Channel G Gain CORR 0x0FC ADC4 Channel H Offset CORR 0x0FE ADC4 Channel H Gain CORR TPMC533 User Manual Issue 1.0.1 Page 78 of 107...
  • Page 79 DAC4 Channel B Gain CORR 0x138 DAC4 Channel C Offset CORR 0x13A DAC4 Channel C Gain CORR 0x13C DAC4 Channel D Offset CORR 0x13E DAC4 Channel D Gain CORR 0x140 to 0x17E Reserved TPMC533 User Manual Issue 1.0.1 Page 79 of 107...
  • Page 80 DAC4 Channel B Gain CORR 0x1B8 DAC4 Channel C Offset CORR 0x1BA DAC4 Channel C Gain CORR 0x1BC DAC4 Channel D Offset CORR 0x1BE DAC4 Channel D Gain CORR 0x1C0 to 0x1FE Reserved TPMC533 User Manual Issue 1.0.1 Page 80 of 107...
  • Page 81 DAC4 Channel B Gain CORR 0x238 DAC4 Channel C Offset CORR 0x23A DAC4 Channel C Gain CORR 0x23C DAC4 Channel D Offset CORR 0x23E DAC4 Channel D Gain CORR 0x240 to 0x27E Reserved TPMC533 User Manual Issue 1.0.1 Page 81 of 107...
  • Page 82 DAC4 Channel B Gain CORR 0x2B8 DAC4 Channel C Offset CORR 0x2BA DAC4 Channel C Gain CORR 0x2BC DAC4 Channel D Offset CORR 0x2BE DAC4 Channel D Gain CORR 0x2C0 to 0x2FE Reserved TPMC533 User Manual Issue 1.0.1 Page 82 of 107...
  • Page 83 DAC4 Channel B Gain CORR 0x338 DAC4 Channel C Offset CORR 0x33A DAC4 Channel C Gain CORR 0x33C DAC4 Channel D Offset CORR 0x33E DAC4 Channel D Gain CORR 0x340 to 0x37E Reserved TPMC533 User Manual Issue 1.0.1 Page 83 of 107...
  • Page 84 DAC4 Channel B Gain CORR 0x3B8 DAC4 Channel C Offset CORR 0x3BA DAC4 Channel C Gain CORR 0x3BC DAC4 Channel D Offset CORR 0x3BE DAC4 Channel D Gain CORR 0x3C0 to 0x7FA Reserved TPMC533 User Manual Issue 1.0.1 Page 84 of 107...

  • Page 85: Table 3-76: Correction Data Rom

    Description Size (Bit) Serial Number 0x7FC Serial Number High Word 0x7FE Serial Number Low Word Table 3-76: Correction Data ROM For the TPMC533-20R the correction values for the DACs are reserved. TPMC533 User Manual Issue 1.0.1 Page 85 of 107...

  • Page 86: O Electrical Interface

    Table 4-2 : ADC Input Schemes If signals without a ground reference shall be connected to TPMC533, connect VIN+ and VIN- to GND with a resistor to prevent the signal source to float out of the ADC’s common-mode range. In most cases the VIN- connection suffices.

  • Page 87: Dac

    The TPMC533 provides up to sixteen analog output channels (DAC Channels) available at the Front I/O Connector. Analog Devices AD5754R are used for the analog outputs. Each AD5754R provides four 16Bit single-ended DAC channels (DAC Channels A-D). • The TPMC533-10R order option provides four AD5754R (DAC1, DAC2, DAC3 & DAC4) →...

  • Page 88: Digital I/O And P14 Back I/O

    Each Digital I/O input is capable of generating an interrupt on either rising edge or falling edge and a debounce filter can be configured to get rid of bounce on the Digital I/O Inputs. TPMC533 User Manual Issue 1.0.1 Page 88 of 107...

  • Page 89: Data Coding

    Midscale – 1LSB -610.35 µV 0xFFFF -FSR + 1LSB -9.999695 V -19.99939 V 0x8001 Full Scale (neg.) -10 V -20 V 0x8000 Table 5-2 : ADC Data Coding, Bipolar Input Range TPMC533 User Manual Issue 1.0.1 Page 89 of 107...

  • Page 90: Dac

    -329.59 µV 0xFFFF -FSR + 1LSB -4.999847 V -9.999695 V -10.79967 V 0x8001 Full Scale (neg.) -5 V -10 V -10.8 V 0x8000 Table 5-4 : DAC Data Coding, Bipolar Output Range TPMC533 User Manual Issue 1.0.1 Page 90 of 107...

  • Page 91: Correction Data

    Value for each ADC Channel and for each DAC Channel at each voltage range. The formula that is applied by the TPMC533 when ADC Data or DAC Data is corrected with the corresponding correction values stored in the Correction Data ROM is: ...

  • Page 92: Operating Modes

    As the Conversion Request bits of all DACs are combined in the Global DAC Control Register, all DAC Channels of the TPMC533 can perform their digital-to-analog conversions simultaneously. Of course, DAC Data must have been written to DAC Data Registers before.

  • Page 93: Sequencer Mode

    DAC Sequencer periodically reads DAC Data, which shall be converted, from Host RAM. The ADC Sequencer and the DAC Sequencer may operate in Normal Mode or Frame Mode, which is configured in the ADC Sequencer Control Register or the DAC Sequencer Control Register. TPMC533 User Manual Issue 1.0.1 Page 93 of 107...

  • Page 94: Normal Mode

    Conversion Clock generation is enabled in the Conversion Signals Generator Enable Register. The first falling Conversion Clock edge after the first rising Conversion Clock edge after the bit is set, triggers the first conversion. Figure 7-2 : Timing in Normal Mode TPMC533 User Manual Issue 1.0.1 Page 94 of 107...

  • Page 95: Frame Mode

    Number of Conversion in the corresponding register; Even if the Number of Conversions is the same for all sequencers. The first falling Conversion Clock edge after the Frame Trigger triggers the first conversion of each frame. Figure 7-4 : Timing in Frame Mode TPMC533 User Manual Issue 1.0.1 Page 95 of 107...

  • Page 96: Sequencer

    Since the TPMC533 can produce/require quite large data volumes when converting at full speed, bulk data transfers to/from the Host RAM Data Buffers are handled with PCI Bus DMA transfers. The TPMC533’s DMA controllers use Block Transfer Mode DMA Cycles.

  • Page 97: Host Ram Data Buffers

    Host RAM Data Buffers For ADC operation the TPMC533 writes the ADC Data to Host RAM via PCI Master DMA transfers. The ADC Data (for all eight ADC Channels of each ADC assigned to the ADC Sequencer) is written to Host RAM Data Buffers.

  • Page 98: Adc

    16bit ADC Data for ADC1 Channel G DMA Buffer Base Address + 0x1E 16bit ADC Data for ADC1 Channel H … … Table 8-1 : Host RAM Data Buffer Example I: Only ADC1 operating in Sequencer Mode TPMC533 User Manual Issue 1.0.1 Page 98 of 107...

  • Page 99: Table 8-2 : Host Ram Data Buffer Example Ii

    DMA Buffer Base Address + 0x3E 16bit ADC Data for ADC2 Channel H … … Table 8-2 : Host RAM Data Buffer Example II: ADC1 and ADC2 are operating in Sequencer Mode TPMC533 User Manual Issue 1.0.1 Page 99 of 107...

  • Page 100: Dac

    DMA Buffer Base Address + 0x1E 16bit DAC Data for DAC2 Channel D … … Table 8-4 : Host RAM Data Buffer Example II: DAC1 and DAC2 are operating in Sequencer Mode TPMC533 User Manual Issue 1.0.1 Page 100 of 107...

  • Page 101: Conversion Signals

    9 Conversion Signals There are three conversion signals: • Conversion Clock 1 • Conversion Clock 2 • Frame Trigger Figure 9-1 : Conversion Signals TPMC533 User Manual Issue 1.0.1 Page 101 of 107...

  • Page 102: Figure 9-2 : Global Conversion Signals Timing Requirements

    ½ T - 250ns GLO_CON_CLK next Global Frame Trigger Event Global Frame Trigger Event to t_setup next Global Conversion Clock 250ns Event Table 9-1 : Global Conversion Signals Timing Requirements TPMC533 User Manual Issue 1.0.1 Page 102 of 107...

  • Page 103: Multi-Board Synchronization

    P14 Back I/O or Front I/O Multi-board Target Card Disabled Output Driver disabled P14 Back I/O or Front I/O Table 9-2 : Generator Enable, Generator Output Driver and Source Selection settings for different System Configurations TPMC533 User Manual Issue 1.0.1 Page 103 of 107...

  • Page 104: Pin Assignment - I/O Connector

    Digital I/O 3 (Global Conversion Clock 2) Digital I/O 4 Digital I/O 5 (Global Frame Trigger) Digital I/O 6 Digital I/O 7 Digital I/O 8 Table 10-1: Pin Assignment Front I/O TPMC533 User Manual Issue 1.0.1 Page 104 of 107...

  • Page 105: P14 Back I/O

    10.2 P14 Back I/O Signal Signal P14 GPIO Global Frame Trigger Global Conversion Clock 2 Global Conversion Clock 1 Table 10-2: Pin Assignment P14 Back I/O TPMC533 User Manual Issue 1.0.1 Page 105 of 107...

  • Page 106: Ta114 Cable

    11 TA114 Cable TEWS TECHNOLOGIES offers a cable with one male HDRA100 connector and two male HD50 connectors which is called TA114. This cable can be used to adapt the TPMC533's Front I/O connection to two more common HD50 connectors.

  • Page 107: X3 Connector

    Digital I/O 4 Digital I/O 3 (Global Conversion Clock 2) Digital I/O 6 Digital I/O 5 (Global Frame Trigger) Digital I/O 8 Digital I/O 7 Table 11-2 : TA114 X3 Connector TPMC533 User Manual Issue 1.0.1 Page 107 of 107...

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