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Tews Technologies TPMC632 Series User Manual

Reconfigurable fpga with 64 ttl i/o / 32 differential i/o lines
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The Embedded I/O Company
TPMC632
Reconfigurable FPGA
with 64 TTL I/O / 32 Differential I/O Lines
Version 1.0
User Manual
Issue 1.0.6
November 2017
TEWS TECHNOLOGIES GmbH
Am Bahnhof 7
25469 Halstenbek, Germany
Phone: +49 (0) 4101 4058 0
Fax: +49 (0) 4101 4058 19
e-mail:
info@tews.com
www.tews.com

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  • Page 1 Reconfigurable FPGA with 64 TTL I/O / 32 Differential I/O Lines Version 1.0 User Manual Issue 1.0.6 November 2017 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek, Germany Phone: +49 (0) 4101 4058 0 Fax: +49 (0) 4101 4058 19 e-mail: info@tews.com...
  • Page 2 Differential Lines, XC6SLX45T-2 Spartan-6 FPGA,128 MB DDR3 TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or use of the TPMC632-13R device described herein. 32 Differential M-LVDS Lines, XC6SLX45T-2...
  • Page 3 Issue Description Date 1.0.0 Initial Issue January 2012 1.0.1 Four further board variants with M-LVDS I/O buffers are January 2013 created 1.0.2 Added chapter “Known Issue” May 2013 1.0.3 Added DDR3 SDRAM Alternative Part May 2015 1.0.4 Added SPI-Flash Alternative Part September 2015 1.0.5 Alternative configurations SPI-Flash assembly...

  • Page 4: Table Of Contents

    Table of Contents PRODUCT DESCRIPTION ................... 7 TECHNICAL SPECIFICATION ..................8 HANDLING AND OPERATION INSTRUCTION ............10 ESD Protection ..........................10 Thermal Considerations ....................... 10 FUNCTIONAL DESCRIPTION ..................11 FPGA Block Diagram ........................11 FPGA .............................. 12 Gigabit Transceiver (GTP) ......................13 Configuration ..........................
  • Page 5 X2 JTAG Header ..........................39 7.4.1 Connector Type ........................39 7.4.2 Pin Assignment ........................39 X3 Debug-Connector ........................40 7.5.1 Connector Type ........................40 7.5.2 Pin Assignment ........................40 KNOWN ISSUES......................41 APPENDIX A ....................... 42 TPMC632 User Manual Issue 1.0.6 Page 5 of 49...
  • Page 6 List of Figures FIGURE 1-1 : BLOCK DIAGRAM ........................7 FIGURE 4-1 : FPGA BLOCK DIAGRAM ......................11 FIGURE 4-2 : GTP BLOCK DIAGRAM ......................13 FIGURE 4-3 : CONFIGURATION SOURCE SELECTION ................14 FIGURE 4-4 : CONFIGURATION DIP-SWITCH SETTINGS ................14 FIGURE 4-5 : JTAG-CHAIN ..........................

  • Page 7: Product Description

    1 Product Description The TPMC632 is a standard single-width 32 bit PMC module providing a user configurable XC6SLX45T-2 or XC6SLX100T-2 Spartan-6 FPGA. The integrated Spartan-6’s PCIe Endpoint Block is connected to a PCIe- to-PCI Bridge which routed to the PMC PCI Interface. Different variants of the TPMC632 provide ESD-protected TTL lines, ESD-protected differential I/O lines and differential Multipoint-LVDS lines.

  • Page 8: Technical Specification

    2 Technical Specification PMC Interface Mechanical Interface PCI Mezzanine Card (PMC) Interface confirming to IEEE P1386/P1386.1 Single Size Electrical Interface PCI Rev. 3.0 compliant 33 MHz or 66 MHz / 32 bit PCI 3.3V and 5V PCI Signaling Voltage On Board Devices PEX8112 (PLX Technology) PCI to PCI Express Bridge PCI Express Endpoint...

  • Page 9: Table 2-1 : Technical Specification

    Temperature Range Operating -40°C to +85°C Storage -40°C to +85°C MTBF TPMC632-10R/-20R: 291000 h TPMC632-11R/-21R: 336000 h TPMC632-12R/-22R: 311000 h TPMC632-13R/-23R: 324000 h TPMC632-14R/-24R: 306000 h MTBF values shown are based on calculation according to MIL-HDBK-217F and MIL-HDBK-217F Notice 2; Environment: G 20°C.

  • Page 10: Handling And Operation Instruction

    3 Handling and Operation Instruction ESD Protection The TPMC632 is sensitive to static electricity. Packing, unpacking and all other handling of the TPMC632 has to be done in an ESD/EOS protected Area. Thermal Considerations Forced air cooling is recommended during operation. Without forced air cooling, damage to the device can occur.

  • Page 11: Functional Description

    4 Functional Description FPGA Block Diagram PCIe to PCI Bridge GPIO: - DIP-Switch Bank 0 - LEDs VCCO = 3.3V - I2C Digital I/O - User LEDs - Debug Header - 64 x Input Spartan-6 - 64 x Output - 64 x O. Enable DDR3 Bank VCCO = 3.3V Bank 2...

  • Page 12: Fpga

    FPGA The FPGA is a Spartan-6 LX45T-2 or LX100T-2 FPGA. Each Spartan-6 FPGA in a FGG484 package provides two Memory Controller Blocks and one Endpoint Block for PCI Express (x1 Linkage). Spartan-6 Slices Flip- DSP48A1 Block CMTs Flops RAM (Kb) Slices Transceivers LX45T...

  • Page 13: Gigabit Transceiver (Gtp)

    Gigabit Transceiver (GTP) The TPMC632 provides one GTP as Spartan-6 PCI Express Endpoint Block. Spartan-6 PCI Interface PCIe X1 Interface Bridge Clock PCIe Clock 100 MHz 125 MHz SI5338 Figure 4-2 : GTP Block Diagram FPGA Signal Connected to Pins MGT0_101 MGTTX B6 / A6...

  • Page 14: Configuration

    Configuration The FPGA can be configured by the following sources: • Platform Flash • SPI-Flash • JTAG The configuration flash can be selected with a DIP-switch; alternatively, JTAG configuration is always available. For the XILINX Platform Flash configuration the Master SelectMAP/BPI mode with 8bit bus width is used.

  • Page 15: Jtag

    4.4.2 JTAG The JTAG-chain is accessible from the JTAG Header, from the Debug Connector or from the PMC-Interface. These interfaces are connected in parallel, so only one connection should be made to avoid signal contentions/possible hardware damage. For direct FPGA configuration, FPGA readback or in-system diagnostics with ChipScope, the JTAG Header can be used to access the JTAG-chain.

  • Page 16: Programming Configuration Devices

    4.4.4 Programming Configuration devices Both user configuration devices XILINX Platform Flash and SPI Flash could be programmed via JTAG interface. The second SPI Flash (TEWS Flash) could not be programmed. For programming the configuration devices the XILINX programming tool iMPACT can be used. An addition JTAG programming hardware is needed (i.e.

  • Page 17: Clocking

    Clocking 4.5.1 FPGA Clock Sources USER_CCLK 32MHz USER_CLK Spartan-6 Si5338 Clock 32MHz MCB_CLK Clock PCIe Clock Figure 4-7 : FPGA Clock Sources The following table lists the available clock sources on the TPMC632: FPGA Clock-Pin Name FPGA Pin Source Description Number MGTREFCLK0_101 A10 / B10...

  • Page 18: I/O Interface

    I/O Interface Each of the 64 digital IO channels are realized with single ended or differential digital buffers. Each channel provides an input; output and an output enable signal which is direct connected to the FPGA device. The IO channels are accessible through the IO Bank 0, Bank 2 and Bank 3 of the Spartan-6 FPGA. The subsequent table lists required I/O setting for correct interfacing.
  • Page 19 FPGA_IN<40># INPUT LVCMOS33 FPGA_IN<41># INPUT LVCMOS33 FPGA_IN<42># INPUT LVCMOS33 FPGA_IN<43># INPUT LVCMOS33 FPGA_IN<44># INPUT LVCMOS33 FPGA_IN<45># INPUT LVCMOS33 FPGA_IN<46># INPUT LVCMOS33 FPGA_IN<47># INPUT LVCMOS33 FPGA_IN<48># INPUT LVCMOS33 FPGA_IN<49># INPUT LVCMOS33 FPGA_IN<50># INPUT LVCMOS33 FPGA_IN<51># INPUT LVCMOS33 FPGA_IN<52># INPUT LVCMOS33 FPGA_IN<53># INPUT LVCMOS33 FPGA_IN<54>#...
  • Page 20 FPGA_OE<27># OUTPUT LVCMOS33 SLOW FPGA_OE<28># OUTPUT LVCMOS33 SLOW FPGA_OE<29># OUTPUT LVCMOS33 SLOW FPGA_OE<30># OUTPUT LVCMOS33 SLOW FPGA_OE<31># OUTPUT LVCMOS33 SLOW FPGA_OE<32># OUTPUT LVCMOS33 SLOW FPGA_OE<33># OUTPUT LVCMOS33 SLOW FPGA_OE<34># OUTPUT LVCMOS33 SLOW FPGA_OE<35># OUTPUT LVCMOS33 SLOW FPGA_OE<36># OUTPUT LVCMOS33 SLOW FPGA_OE<37># OUTPUT LVCMOS33...

  • Page 21: Table 4-6 : Digital I/O Interface

    FPGA_OUT<15># OUTPUT LVCMOS33 SLOW FPGA_OUT<16># OUTPUT LVCMOS33 SLOW FPGA_OUT<17># OUTPUT LVCMOS33 SLOW FPGA_OUT<18># OUTPUT LVCMOS33 SLOW FPGA_OUT<19># OUTPUT LVCMOS33 SLOW FPGA_OUT<20># OUTPUT LVCMOS33 SLOW FPGA_OUT<21># OUTPUT LVCMOS33 SLOW FPGA_OUT<22># OUTPUT LVCMOS33 SLOW FPGA_OUT<23># OUTPUT LVCMOS33 SLOW FPGA_OUT<24># OUTPUT LVCMOS33 SLOW FPGA_OUT<25># OUTPUT LVCMOS33...

  • Page 22: Memory

    Memory The TPMC632 is equipped with a 128 Mbytes, 16 bit wide DDR3 SDRAM and a 32-Mbit non-volatile SPI- Flash. The SPI-Flash can also be used as configuration memory. 4.7.1 DDR3 SDRAM The TPMC632 provides a MT41J64M16 or MT41K64M16 (96-ball) DDR3 memory device. The memory is accessible through the Memory Controller Block hard-IPs in bank 1 of the Spartan-6 FPGA.

  • Page 23: Table 4-7 : Ddr3 Sdram Interface

    Signal I/O Standard Termination Memory Device Bank A Name FPGA SSTL15_II SSTL15_II SSTL15_II SSTL15_II SSTL15_II SSTL15_II SSTL15_II SSTL15_II DQ10 SSTL15_II DQ10 DQ11 SSTL15_II DQ11 DQ12 SSTL15_II DQ12 DQ13 SSTL15_II DQ13 DQ14 SSTL15_II DQ14 DQ15 SSTL15_II DQ15 LDQS DIFF_SSTL15_II LDQS LDQS# DIFF_SSTL15_II LDQS# UDQS...

  • Page 24: Spi-Flash

    4.7.2 SPI-Flash The TPMC632 provides two Winbond W25Q32 32-Mbit serial Flash memory, one of these Flash can be used as FPGA configuration source. The second serial Flash contains configurable TPMC632 FPGA Example design. The TPMC632 could be delivered with the W25Q32FV or the W25Q32JV. In contrast to the W25Q32FV EEPROM, the W25Q32JV EEPPROM does not support the QPI mode.

  • Page 25: User Gpio

    User GPIO The TPMC632 has some general purpose I/O and debug signals connected to FPGA Bank 1. The required signaling standard is LVCMOS15, due to Memory Controller Block usage. Two pins of the FPGA are routed to the Debug Connector for use as debug interface (UART). This is not a real RS-232 interface.

  • Page 26: On Board Indicators

    On Board Indicators The TPMC632 provides a couple of board-status LEDs as shown below. These include Power-Good and FPGA configuration status indications as well as four general purpose LEDs. Board Status LEDs Color Description PGOOD Green Power Good Signal for all on board power supplies. DONE FPGA DONE-Pin LED Indicates successful FPGA configuration...

  • Page 27: Design Help

    5 Design Help Example Design User applications for the TPMC632 can be developed using the design software ISE WebPACK which can be downloaded free of charge from www.xilinx.com. TEWS offers an FPGA Development Kit (TPMC632-FDK) which consists of well documented basic example design.

  • Page 28: Installation

    6 Installation Pull Up Voltage The voltage of the pull up resistors can be either 3.3V, 5V or alternatively GND, specified by jumper J1. The default pull up voltage is 5V. J1 Jumper Position Pull (Up) Voltage 1 – 3 3.3V 3 –...

  • Page 29: I/O Interface

    I/O Interface 6.2.1 TTL I/O Interface Each of the 64 (TPMC632x0) or 32 (TPMC632x2) TTL I/O line contains two 74LVT126 bus buffers as an interface to the FPGA pins. The logic levels of the buffers are TTL compatible, meaning that the minimum high level is 2.0V and the maximum low level is 0.8V.

  • Page 30: Differential I/O Interface

    6.2.2 Differential I/O Interface Each of the 32 (TPMC632-x1R) or 16 (TPMC632-x2R) differential I/O line pairs is connected on the one side with an input, output and output enable pin at the XILINX FPGA. On the other side connected to a MAX3078E, an ESD-protected RS485/RS422 transceiver and a 120Ω...

  • Page 31: Back I/O Configuration

    Back I/O Configuration The configuration of P14 64 pin Mezzanine “Back I/O” connector lines [57..64] can be changed to ground instead of IO_56 .. IO_63 signals by change of zero ohm resistors. The TPMC632 is sensitive to static electricity. Packing, unpacking and all other handling of the TPMC632 has to be done in an ESD/EOS protected Area.

  • Page 32: Figure 6-6 : Jumper Positions For Back I/O Options

    Back I/O Line Signal Jumper Position ground R288 IO_56 / IO_28- (default) R291 ground R289 I/O_57 / IO_28+ (default) R292 ground R279 I/O_58 / IO_29- (default) R284 ground R287 I/O_59 / IO_29+ (default) R290 ground R277 I/O_60 / IO_30- (default) R282 ground R278...

  • Page 33: Fpga Debug Connector

    FPGA Debug Connector The Debug Connector (X3) of the TPMC632 can be used to connect a debug adapter, if necessary. The debug adapter must be connected to the TPMC632 prior to PMC-Carrier installation. It is recommended to use the TEWS TA900 Debug Adapter. The Debug Connector provides three logical interfaces: JTAG, FPGA-UART and one General Purpose User Signal (GPIO_BUT).

  • Page 34: Fpga Jtag Connector

    FPGA JTAG Connector The FPGA JTAG connector X2 lets the user directly connect a JTAG interface cable to the on board JTAG chain, e.g. for FPGA read back and real-time debugging of the FPGA design (using Xilinx “ChipScope”). A through hole, right angle 90° connector with 7 x 2 pins and 2 mm pitch is mounted (Molex 0877601416 or compatible).

  • Page 35: Pin Assignment - I/O Connector

    7 Pin Assignment – I/O Connector Overview X1 Front Panel I/O Connector Pin 34 Pin 1 Pin 68 Pin 35 Figure 7-1 : Front Panel I/O Connector Numbering 7.2.1 Connector Type Pin-Count Connector Type HD68 SCSI-3 type female connector Source & Order Info AMP 787082-7 or compatible TPMC632 User Manual Issue 1.0.6 Page 35 of 49...

  • Page 36: Pin Assignment

    7.2.2 Pin Assignment -x0R -x1R / -x3R -x2R / -x4R -x0R -x1R / -x3R -x2R / -x4R IO_0 IO_0- IO_0- IO_1 IO_0+ IO_0+ IO_2 IO_1- IO_1- IO_3 IO_1+ IO_1+ IO_4 IO_2- IO_2- IO_5 IO_2+ IO_2+ IO_6 IO_3- IO_3- IO_7 IO_3+ IO_3+ IO_8 IO_4-...

  • Page 37: Back I/O Pmc Connector P14

    Back I/O PMC Connector P14 7.3.1 Connector Type Pin-Count Connector Type 64 pol. Mezzanine SMD Connector Source & Order Info Molex – 71436-2864 or compatible 7.3.2 Pin Assignment -x0R -x1R / -x3R -x2R / -x4R -x0R -x1R / -x3R -x2R / -x4R IO_0 IO_0- IO_0-...

  • Page 38: Table 7-2 : Pin Assignment Back I/O Pmc Connector P14

    -x0R -x1R / -x3R -x2R / -x4R -x0R -x1R / -x3R -x2R / -x4R IO_29 IO_14+ IO_14+ IO_61 IO_30+ IO_61 IO_30 IO_15- IO_15- IO_62 IO_31- IO_62 IO_31 IO_15+ IO_15+ IO_63 IO_31+ IO_63 Table 7-2 : Pin Assignment Back I/O PMC Connector P14 TPMC632 User Manual Issue 1.0.6 Page 38 of 49...

  • Page 39: X2 Jtag Header

    X2 JTAG Header This header directly connects a JTAG interface cable to the JTAG pins to the on board JTAG chain. The pinout of this header matches the pinout of the Xilinx Platform Cable USB II. This allows the direct usage of Xilinx software-tools like Chipscope or iMPACT with the Platform Cable USB II.

  • Page 40: X3 Debug-Connector

    X3 Debug-Connector 7.5.1 Connector Type Pin-Count Connector Type 20-pin, 1 mm FPC (Flexible Printed Circuit) Connector AMP 2-487951-0 / 2-84953-0 or Source & Order Info Molex 0522072060 7.5.2 Pin Assignment Signal Description JTAG SEL A 4.7k pullup to 3.3 Volt is located on the TPMC632 3.3V JTAG reference I/O voltage Test Data Output (Input at JTAG Interface)

  • Page 41: Known Issues

    8 Known Issues Level Switching at TPMC632 I/O Lines during FPGA Configuration. At power-up or after a FPGA reconfiguration is started, the FPGA need up to 10ms to start configuration. During this time, the I/O lines of the TPMC632 may randomly toggle between high and low in case that I/O Line 19 of the TPMC632 (X1 pin 45 resp.
  • Page 42 Simulation Tool : Xilinx ISIM included in Design Tool Description : The file lists all FPGA pins that are connected on the TPMC632 Owner : TEWS TECHNOLOGIES GmbH Am Bahnhof 7 D-25469 Halstenbek Tel.: +49 / (0)4101 / 4058-0 Fax.: +49 / (0)4101 / 4058-19 e-mail: support@tews.com...
  • Page 43 config prohibit = "Y4"; # INIT_B Bank 2 config prohibit = "AA3"; # CSO_B Bank 2 config prohibit = "AB2"; # PROGRAM_B Bank 2 config prohibit = "AA12"; # D14 Bank 2 ## ############################################################################################# ## ## Section: SPI ## ############################################################################################# ## # Define I/O Standard net "MISO[*]"...
  • Page 44 net "FPGA_OE[18]" loc = "C1"; # Bank 3 net "FPGA_OE[19]" loc = "M8"; # Bank 3 net "FPGA_OE[20]" loc = "AA18"; # Bank 2 net "FPGA_OE[21]" loc = "AB18"; # Bank 2 net "FPGA_OE[22]" loc = "U14"; # Bank 2 net "FPGA_OE[23]"...
  • Page 45 net "FPGA_IN[15]" loc = "Y1"; # Bank 3 net "FPGA_IN[16]" loc = "Y14"; # Bank 2 net "FPGA_IN[17]" loc = "Y15"; # Bank 2 net "FPGA_IN[18]" loc = "B2"; # Bank 0 net "FPGA_IN[19]" loc = "C3"; # Bank 0 net "FPGA_IN[20]"...
  • Page 46 net "FPGA_OUT[16]" loc = "T5"; # Bank 3 net "FPGA_OUT[17]" loc = "M1"; # Bank 3 net "FPGA_OUT[18]" loc = "D2"; # Bank 3 net "FPGA_OUT[19]" loc = "J7"; # Bank 3 net "FPGA_OUT[20]" loc = "F1"; # Bank 3 net "FPGA_OUT[21]"...
  • Page 47 net "DDR_A[*]" iostandard = SSTL15_II; # 1.5V net "DDR_BA[*]" iostandard = SSTL15_II; # 1.5V net "DDR_?DQS_?" iostandard = DIFF_SSTL15_II; # 1.5V net "DDR_CK_?" iostandard = DIFF_SSTL15_II; # 1.5V net "DDR_CKe" iostandard = SSTL15_II; # 1.5V net "DDR_RAS_n" iostandard = SSTL15_II; # 1.5V net "DDR_CAS_n"...
  • Page 48 net "DDR_RZQ" loc = "F18"; # Bank 1 net "DDR_ZIO" loc = "P19"; # Bank 1 # Additional Constratints config mcb_performance = standard; # General MCB constraints ## ############################################################################################# ## ## Section: Clocking ## ############################################################################################# ## # Define I/O Standards net "CLKGEN_S*"...
  • Page 49 # Location Constraints net "FPGA_SW_n" loc = "Y11"; # Bank 2 net "FPGA_RST_n" loc = "AA14"; # Bank 2 ## ############################################################################################# ## ## Section: General Purpose I/O ## ############################################################################################# ## # Define I/O Standards net "GPIO_LED[?]" iostandard = LVCMOS15; # Bank 1 Supply 1.5V net "GPIO_T*"...

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