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The Embedded I/O Company
TEWS TECHNOLOGIES GmbH
Am Bahnhof 7
Phone: +49-(0)4101-4058-0
e-mail: info@tews.com
TPMC671
16 Digital Inputs (24V)
16 Digital Outputs (24V, 0.5A)
Version 1.0
User Manual
Issue 1.1
October 2004
25469 Halstenbek / Germany
Fax: +49-(0)4101-4058-19
www.tews.com
TEWS TECHNOLOGIES LLC
1 E. Liberty Street, Sixth Floor
Phone: +1 (775) 686 6077
e-mail: usasales@tews.com
Reno, Nevada 89504 / USA
Fax: +1 (775) 686 6024
www.tews.com
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Summary of Contents for Tews Technologies TPMC671
- Page 1 16 Digital Inputs (24V) 16 Digital Outputs (24V, 0.5A) Version 1.0 User Manual Issue 1.1 October 2004 TEWS TECHNOLOGIES GmbH TEWS TECHNOLOGIES LLC Am Bahnhof 7 25469 Halstenbek / Germany 1 E. Liberty Street, Sixth Floor Reno, Nevada 89504 / USA...
- Page 2 I/O in this document at any time without notice. TEWS TECHNOLOGIES GmbH is not liable for any TPMC671-20 damage arising out of the application or use of the device described herein.
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Page 3: Table Of Contents
7.2 Output Wiring High Side Switch (-10 / -20) .................26 7.3 Output Wiring Low Side Switch (-11 / -21)..................26 PIN ASSIGNMENT – I/O CONNECTOR ..............27 8.1 Front Panel Connector .........................27 8.2 Mezzanine Card Connector P14 ....................28 TPMC671 User Manual Issue 1.1 Page 3 of 28... - Page 4 FIGURE 5-1 : PCI9030 HEADER........................19 FIGURE 5-2 : PCI9030 PLD BASE ADDRESS USAGE.................20 FIGURE 5-3 : PCI9030 LOCAL CONFIGURATION REGISTER ..............21 FIGURE 5-4 : CONFIGURATION EEPROM TPMC671-XX ................22 FIGURE 6-1 : LOCAL BUS LITTLE/BIG ENDIAN...................24 FIGURE 7-1 : INPUT WIRING.........................26 FIGURE 7-2 : OUTPUT WIRING HIGH SIDE SWITCH..................26...
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Page 5: Product Description
The TPMC671 has 16 digital high side or low side switches (build option) with galvanic isolation from the computer system by optocouplers. The outputs are isolated against each other in groups of four outputs. -
Page 6: Technical Specification
200 mA typical @ +3.3V DC with all inputs and outputs active Operating -25 °C to +85 °C Temperature Range Storage -55°C to +125°C MTBF 252000 h Humidity 5 – 95 % non-condensing Weight 72 g Figure 2-1 : Technical Specification TPMC671 User Manual Issue 1.1 Page 6 of 28... -
Page 7: Functional Description
3.1 Digital Outputs 3.1.1 Optical Isolation The TPMC671 has 16 high side switch (TPMC671-10/20) or 16 low side switch (TPMC671-11/21) digital outputs. The standard signal level for these outputs is 24V DC. All outputs are isolated by optocouplers from the computer system and are also isolated against each other in groups of four outputs. -
Page 8: Output Watchdog
3 of Global Control Register. Any software access (read or write) to the Data Output Register of the TPMC671 will retrigger the watchdog. The maximum time between two accesses is set to 120ms, if the time expires without a software access all outputs go into the ‘OFF’... -
Page 9: Local Space Addressing
Rising Edge Interrupt Enable Register 0x08 Falling Edge Interrupt Enable Register 0x0A Rising Edge Interrupt Status Register 0x0C Falling Edge Interrupt Status Register 0x0E Debounce Time Register Figure 4-2 : FPGA Register Space TPMC671 User Manual Issue 1.1 Page 9 of 28... -
Page 10: Data Output Register
OUTPUT6 output line 16. OUTPUT5 After power-on or reset the Data Output Register is OUTPUT4 cleared to ‘0’, all outputs are inactive. OUTPUT3 OUTPUT2 OUTPUT1 Figure 4-3 : Data Output Register TPMC671 User Manual Issue 1.1 Page 10 of 28... -
Page 11: Data Input Register
1 : Input line is logic high INPUT9 INPUT8 INPUT7 Bit 0 represents Input Line 1 and bit 15 represents the Input Line 16. INPUT6 INPUT5 INPUT4 INPUT3 INPUT2 INPUT1 Figure 4-4 : Data Input Register TPMC671 User Manual Issue 1.1 Page 11 of 28... -
Page 12: Control / Status Register
Additional to this Global Interrupt Enable the Interrupt INTA# must be enabled in the PCI Interrupt Line Register (PCIILR; 0x3C) of the PCI Controller PCI9030. Default after power-on and reset is: INTA# is enabled. The watchdog status is only active if the watchdog is enabled. TPMC671 User Manual Issue 1.1 Page 12 of 28... -
Page 13: Rising Edge Interrupt Enable Register
INT_ENA_H7 Bit 15 enables interrupt of input line 16 for rising edge. INT_ENA_H6 All other bits are equivalent. INT_ENA_H5 INT_ENA_H4 INT_ENA_H3 INT_ENA_H2 INT_ENA_H1 Figure 4-6 : Rising Edge Interrupt Enable Register TPMC671 User Manual Issue 1.1 Page 13 of 28... -
Page 14: Falling Edge Interrupt Enable Register
INT_ENA_L7 Bit 15 enables interrupt of input line 16 for falling edge. INT_ENA_L6 All other bits are equivalent. INT_ENA_L5 INT_ENA_L4 INT_ENA_L3 INT_ENA_L2 INT_ENA_L1 Figure 4-7 : Falling Edge Interrupt Enable Register TPMC671 User Manual Issue 1.1 Page 14 of 28... -
Page 15: Rising Edge Interrupt Status Register
An interrupt request for a specific input line is cleared INT_STA_H2 by writing ‘1’ to the according bit of the Rising Edge Interrupt Status Register. INT_STA_H1 Figure 4-8 : Rising Edge Interrupt Status Register TPMC671 User Manual Issue 1.1 Page 15 of 28... -
Page 16: Falling Edge Interrupt Status Register
An interrupt request for a specific input line is cleared INT_STA_L2 by writing ‘1’ to the according bit of the Falling Edge INT_STA_L1 Interrupt Status Register. Figure 4-9 : Falling Edge Interrupt Status Register TPMC671 User Manual Issue 1.1 Page 16 of 28... -
Page 17: Debounce Time Register
PCICLK - 33.33 MHz - max. debounce time [ s ] ⋅ ⋅ PCICLK - min. debounce time [ s ] ⋅ ⋅ PCICLK Figure 4-11: Formulas to determine preload value TPMC671 User Manual Issue 1.1 Page 17 of 28... -
Page 18: Figure 4-12: Debounce Time / Examples
± 35.714 250.000 37201 0x9151 ± 42.856 300.000 44641 0xAE61 ± 50.000 350.000 52082 0xCB72 ± 57.142 400.000 59522 0xE882 ± 62.915 440.402 65535 0xFFFF Figure 4-12: Debounce Time / Examples TPMC671 User Manual Issue 1.1 Page 18 of 28... -
Page 19: Pci9030 Target Chip
VPD Address VPD Nxt Cap. VPD Cap. ID Y[31:16] 0000 00 03 0x50 VPD Data 00000000 Figure 5-1 : PCI9030 Header Subsystem ID: TPMC671-10: 0x000A TPMC671-11: 0x000B TPMC671-20: 0x0014 TPMC671-21: 0x0015 TPMC671 User Manual Issue 1.1 Page 19 of 28... -
Page 20: Pci Base Address Initialization
0x14 PCI9030 LCR’s I/O Used 0x18 PCI9030 Local Space 0 Used 0x1C PCI9030 Local Space 1 Not used 0x30 Expansion ROM Not used Figure 5-2 : PCI9030 PLD Base Address Usage TPMC671 User Manual Issue 1.1 Page 20 of 28... -
Page 21: Local Configuration Register (Lcr)
Miscellaneous Control Register 0x0078_0000 0x54 General Purpose I/O Control 0x0249_2492 0x70 Hidden1 Power Management data select 0x0000_0000 0x74 Hidden 2 Power Management data scale 0x0000_0000 Figure 5-3 : PCI9030 Local Configuration Register TPMC671 User Manual Issue 1.1 Page 21 of 28... -
Page 22: Configuration Eeprom
0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xF0 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF Figure 5-4 : Configuration EEPROM TPMC671-xx Subsystem-ID Value (Offset 0x0C): TPMC671-10: 0x000A TPMC671-11: 0x000B TPMC671-20: 0x0014 TPMC671-21: 0x0015 TPMC671 User Manual Issue 1.1 Page 22 of 28... -
Page 23: Local Software Reset
PCI9030 remains in this reset condition until the PCI Host clears this bit. The contents of the PCI9030 PCI and Local Configuration Registers are not reset. The PCI9030 PCI Interface is not reset. TPMC671 User Manual Issue 1.1 Page 23 of 28... -
Page 24: Configuration Hints
Byte 0 D[15..8] Byte 1 D[7..0] 8 Bit upper lane 8 Bit Byte 0 D[31..24] Byte 0 D[7..0] 8 Bit lower lane Byte 0 D[7..0] Figure 6-1 : Local Bus Little/Big Endian TPMC671 User Manual Issue 1.1 Page 24 of 28... - Page 25 24 of the according register sets the Mode. A value of 1 indicates Big Endian and a value of 0 indicates Little Endian. For further information please refer to the PCI9030 manual which is also part of the TPMC671-ED Engineering Documentation.
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Page 26: Installation
7.2 Output Wiring High Side Switch (-10 / -20) Figure 7-2 : Output Wiring High Side Switch 7.3 Output Wiring Low Side Switch (-11 / -21) Figure 7-3 : Output Wiring Low Side Switch TPMC671 User Manual Issue 1.1 Page 26 of 28... -
Page 27: Pin Assignment - I/O Connector
Figure 8-1 : Pin Assignment I/O HD68 SCSI-3 type Connector Please check the maximum current of the used connection cable. Some standard cables (AWG28 68pin) are limited to 0.75 A per lead. TPMC671 User Manual Issue 1.1 Page 27 of 28... -
Page 28: Mezzanine Card Connector P14
Figure 8-2 : Mezzanine Card Connector P14 Please verify that the tracks from the P14 connector to the Px connector of the PMC carrier board are designed for a current of typical 0.5 A min per output. TPMC671 User Manual Issue 1.1 Page 28 of 28...
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