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TXMC639
Tews Technologies TXMC639 Manuals
Manuals and User Guides for Tews Technologies TXMC639. We have
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Tews Technologies TXMC639 manual available for free PDF download: User Manual
Tews Technologies TXMC639 User Manual (95 pages)
Reconfigurable FPGA with 16 x 16 bit Analog Input, 8 x 16 bit Analog Output and 32 digital I/O
Brand:
Tews Technologies
| Category:
I/O Systems
| Size: 4 MB
Table of Contents
Table of Contents
4
1 Product Description
9
2 Technical Specification
10
Table 2-1 : Technical Specification
11
3 Handling and Operation Instruction
12
ESD Protection
12
Thermal Considerations
12
4 Pci Device Topology
13
Figure 4-1 : Pcie/Pci Device Topology
13
Table 4-1 : On-Board Pcie / Pci Devices
13
BCC (Board Configuration Controller) FPGA
14
PCI BAR Overview
14
PCI Configuration Registers (PCR)
14
Table 4-2 : Pci Configuration Registers
14
Table 4-3 : Pci Bar Overview
14
Local Configuration Register Space
15
Table 4-4 : Local Configuration Register Space
15
In-System Programming Data Space
16
User FPGA (Kintex TM 7)
14
5 Register Description
17
User FPGA (Kintex TM 7)
17
BCC (Board Configuration Controller) FPGA
18
DAC and ADC Control / Status Register - 0X00
18
Table 5-1 : Dac Control and Status Register
19
DAC Output Voltage Range Register - 0X04
20
ADC Input Voltage Range Register - 0X08
20
Table 5-2 : Dac Output Voltage Range Register
20
Table 5-3 : Adc Input Voltage Range Register
20
Reference DAC Voltage Control Register - 0X10 to 0X4C
21
Figure 5-1 : Dac and Ref. Dac Schemata
21
Figure 5-2 : Dac Output Channel
21
Table 5-4 : Reference Dac Voltage Control Register
21
Table 5-5 : Voltage Coding for the Reference Dac
22
Digital I/O Interface Configuration /Status Register - 0X60
23
Table 5-6 : I/O Pull-Resistor Configuration Register
24
TXMC639 I/O Area Temperature Sensor Register - 0X64
25
Table 5-7 : Txmc639 I/O Area Temperature Sensor Register
25
User FPGA JTAG Control and Status Register - 0X80
26
Table 5-8 : User Fpga Jtag Control and Status Register
26
User FPGA JTAG Signal Line Register - 0X84
27
User FPGA JTAG TMS Data Register - 0X88
28
User FPGA JTAG TDI Data Register - 0X8C
28
Table 5-9 : User Fpga Jtag Signal Line Register
28
Table 5-10 : User Fpga Jtag Tms Data Register
28
Table 5-11 : User Fpga Jtag Tdi Data Register
28
User FPGA JTAG TDO Data Register - 0X90
29
I2C Bridge Register - 0Xa0
29
Interrupt Enable Register - 0Xc0
29
Table 5-12 : User Fpga Jtag Tdo Data Register
29
Table 5-13 : I2C Bridge Register
29
Table 5-14 : Interrupt Enable Register
29
Interrupt Status Register - 0Xc4
30
Table 5-15 : Interrupt Status Register
30
User FPGA Configuration Control/Status Register - 0Xd0
31
Table 5-16 : User Fpga Configuration Control/Status Register
31
User FPGA Configuration Data Register - 0Xd4
32
ISP Control Register - 0Xe0
32
Table 5-17 : User Fpga Configuration Data Register
32
Table 5-18 : Isp Control Register
32
ISP Configuration Register - 0Xe4
33
ISP Command Register - 0Xe8
33
Table 5-19 : Isp Configuration Register
33
Table 5-20 : Isp Command Register
33
ISP Status Register - 0Xec
34
Table 5-21 : Isp Status Register
34
TXMC639 Board Temperature Sensor Register - 0Xf4
35
TXMC639 Serial Number Register - 0Xf8
35
BCC - FPGA Code Version - 0Xfc
35
Table 5-22 : Txmc639 Board Temperature Sensor Register
35
Table 5-23 : Txmc639 Serial Number Register
35
Table 5-24: Bcc - Fpga Code Version
35
6 Interrupts
36
Interrupt Sources
36
User FPGA (Kintex TM 7)
36
Bcc
36
Interrupt Handling
36
7 Functional Description
37
User FPGA Block Diagram
37
Figure 7-1 : Fpga Block Diagram
37
User FPGA Highlights
38
Table 7-1 : Txmc639 Fpga Feature Overview
38
Table 7-2 : Fpga Bank Usage
38
User FPGA Gigabit Transceiver (MGT)
39
Figure 7-2 : User Fpga Mgt Block Diagram
39
Table 7-3 : User Fpga Mgt Connections
39
Table 7-4 : User Fpga Mgt Reference Clocks
40
User FPGA Configuration
41
Master Serial SPI Flash Configuration
41
Manually User FPGA SPI Flash Reconfiguration
42
Slave Select Map Configuration
43
Configuration Via JTAG
45
User JTAG Chain
45
TEWS Factory JTAG Chain
45
Figure 7-3 : User Jtag-Chain
45
Figure 7-4 : Tews Factory Jtag-Chain
45
Programming User FPGA SPI Configuration Flash
46
Erasing User FPGA SPI Configuration Flash
47
Sector Erasing User FPGA SPI Configuration Flash
48
Reading User FPGA SPI Configuration Flash
49
BCC (Board Configuration Controller) FPGA
50
I2C Interface to BCC Register
50
Table 7-5: User Fpga I2C Interface to Bcc
50
Clocking
51
FPGA Clock Sources
51
Figure 7-5 : Fpga Clock Sources
51
Table 7-6 : Available Fpga Clocks
52
Serial ADC Interface
53
Overview
53
Figure 7-6 : Analog Input Section
53
Figure 7-7 : Analog Input Block Diagram
53
ADC Digital Output Coding
54
ADC Data Coding ±20.56 V Voltage Range
54
Table 7-7: Adc Max Differential Voltages
54
Table 7-8: Adc Data Coding
54
ADC Data Coding ±10.28 V Voltage Range
55
ADC Data Coding ±5.14 V Voltage Range
55
User FPGA Pinning
56
Programming Hints LTC2320-16
57
Figure 7-8 : Digital Adc to Fpga Interface
57
Figure 7-9 : Timing Diagram Ltc2320-16 Ddr-Mode (2 Channels Per Sdo Pair)
57
Parallel DAC Interface
58
Overview
58
Output Voltage Range
58
Figure 7-10 : Analog Output Section
58
Figure 7-11 : Analog Output Section
58
User FPGA Pinning
59
Table 7-9: Txcm639 Parallel Dac Interface
59
Programming Hints for AD5547
60
TTL I/O Interface
61
Figure 7-12 : One Channel Ttl I/O Interface
61
User FPGA Pinning
62
Table 7-10 : User Fpga Ttl Io and Oe Pins
63
RS422 Interface
64
RS422 FPGA Interface
64
Figure 7-13 : 1 Channel Digital I/O Multiplexer Block Diagram
64
Figure 7-14 : One Channel Rs422 I/O Interface
64
User FPGA Pinning
65
Table 7-11 : User Fpga Rs422 Interface Pins
66
I/O Pull Configuration
67
Table 7-12: I/O Pull Configuration
67
Table 7-13 : User Fpga Pins
67
Memory
68
Ddr3 Sdram
68
Table 7-14 : Ddr3 Sdram Interface
69
SPI-Flash
71
I2C - Eeprom
71
Table 7-15 : Fpga Spi-Flash Connections
71
Table 7-16: Fpga I2C Eeprom Connections
71
ADC and DAC Ccorrectable Errors
72
ADC Correction Values
72
Table 7-17: Adc Correction Values
73
DAC Corretion Values
74
Table 7-18: Dac Correction Data Values
75
ADC Data Correction Formula
76
DAC Data Correction Formula
76
DAC and ADC Voltage Ranges
77
Table 7-19: Adc and Dac Voltage Ranges
79
Table 7-20: Version of Eeprom Data Structure
79
Rear I/O Interface
80
Table 7-21 : Digital Rear I/O Interface
81
Digital Interface to XMC P16 Connector
82
Table 7-22 : XMC P16 Digital I/O Interface
82
JTAG Controller to User FPGA JTAG Interface
83
Version of EEPROM Data Structure
79
Bit-IO
83
Vector-IO
83
I2C Bridge
84
Figure 7-15 : User Fpga I2C to Bcc I2C Bridge
84
On-Board Indicators
85
Table 7-23: Board-Status and User Leds
85
User FPGA LED Pinning
86
User FPGA Reset Inputs
86
Table 7-24: Txmc639 User On-Board Indicators
86
Table 7-25: User Fpga Reset Inputs
86
8 Design Help
87
Board Reference Design
87
9 O Interfaces
88
Front I/O - ADC Analog Input Level
88
Table 9-1 : Differential Input Voltage
88
Front I/O - Analog Output Level
89
Rear I/O Interface
89
Figure 9-1 : Dac Output Interface
89
Table 9-2 : Dac Electrical Interface
89
10 O Description
90
Overview
90
Front I/O Connector (X1)
91
Figure 10-1 : Front Panel I/O Connector Numbering
91
Table 10-1: Pin Assignment Front Panel I/O Connector
92
Rear I/O Connector (P14)
93
Figure 10-2 : Pin Assignment P14 Rear I/O Connector
93
Rear I/O Connector (P16)
94
Figure 10-3 : Pin Assignment P16 Rear I/O Connector
94
FPGA JTAG Header (X2)
95
Table 10-2: Pin Assignment Jtag Header
95
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