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Summary of Contents for Tews Technologies TPMC160
- Page 1 The Embedded I/O Company TPMC160 Automotive Sensor Simulator Version 1.0 User Manual Issue 1.0.2 July 2022 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek, Germany Phone: +49 (0) 4101 4058 0 Fax: +49 (0) 4101 4058 19 e-mail: info@tews.com www.tews.com...
- Page 2 GmbH reserves the right to change the product described in this document at any time without notice. TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or use of the device described herein. 2022 by TEWS TECHNOLOGIES GmbH All trademarks mentioned are property of their respective owners.
- Page 3 - The Protocol Setup Examples were revised. 1.0.2 - Description of the Board health register has been improved July 2022 - The description of the interrupt status registers was added - Corrected I/O Connector description TPMC160 User Manual Issue 1.0.2 Page 3 of 63...
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Page 4: Table Of Contents
Cycle Counter Match Register Ch2-3 0x378 .............. 41 5.3.8.2.3 Cycle Counter Match Register Ch4-5 0x37C ............. 41 5.3.8.2.4 Cycle Counter Match Register Ch6-7 0x380 .............. 41 5.3.8.3 Cycle Counter Value Registers 0x384 – 0x390 ..............42 TPMC160 User Manual Issue 1.0.2 Page 4 of 63... - Page 5 “PWM” ..........................59 7.2.1.3 “AK-Protocol” or “VDA” ...................... 60 7.2.1.4 Custom Protocol ........................ 60 7.2.2 PSI5 ............................61 PIN ASSIGNMENT – I/O CONNECTOR ..............62 Front Panel I/O Connector ......................62 TPMC160 User Manual Issue 1.0.2 Page 5 of 63...
- Page 6 TABLE 5-24 : PSI5 FIFO STATUS REGISTER ....................37 TABLE 5-25 : PSI5 SYNC DATA REGISTERS....................37 TABLE 5-26 : CYCLE COUNTER CONTROL REGISTER ................40 TABLE 5-27 : CYCLE COUNTER MATCH REGISTER CH0-1 ..............41 TPMC160 User Manual Issue 1.0.2 Page 6 of 63...
- Page 7 TABLE 7-1 : CHANNEL SIGNAL LINES TO FPGA ..................57 TABLE 7-2 : CURRENT SINK CHARACTERISTICS ..................57 TABLE 7-3 : VOLTAGE MONITOR CHARACTERISTICS ................58 TABLE 8-1 : PIN ASSIGNMENT FRONT I/O CONNECTOR ................. 63 TPMC160 User Manual Issue 1.0.2 Page 7 of 63...
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Page 8: Product Description
1 Product Description The TPMC160 is a standard single-width 32 bit PMC module and supports a 33 MHz / 32-bit universal (5 V / 3.3 V) PCI interface. The TPMC160 offers eight isolated automotive sensor simulator channels, which can act as a PSI5 or as wheel speed sensor. -
Page 9: Technical Specification
If FIT rates are not available, MIL-HDBK-217F and MIL-HDBK-217F Notice 2 formulas are used for FIT rate calculation. Humidity 5 – 95 % non-condensing Weight 77 g Table 2-1 : Technical Specification TPMC160 User Manual Issue 1.0.2 Page 9 of 63... -
Page 10: Handling And Operation Instructions
Packing, unpacking and all other module handling has to be done with appropriate care. Power Dissipation This PMC module requires adequate forced air cooling! Ground for Isolated I/O I/O Connector's isolated ground signals must be connected to external ground. TPMC160 User Manual Issue 1.0.2 Page 10 of 63... -
Page 11: Terms And Definitions
For future software compatibility: For register write access reserved bits shall be written ‘0’. Style Conventions Hexadecimal characters are specified with prefix 0x (i.e. 0x029E). For signals on hardware products, "Active Low" is represented by the signal name with an added # (i.e. IP_RESET#). TPMC160 User Manual Issue 1.0.2 Page 11 of 63... -
Page 12: Pci Interface
0x094 - 0x0AC Reserved Square Wave Protocol Registers 0x0B0 - 0x0CC SWP Cycle Registers 0x0D0 - 0x11C Reserved PWM Protocol Registers 0x120 - 0x13C PWM Cycle Registers 0x140 - 0x15C Reserved TPMC160 User Manual Issue 1.0.2 Page 12 of 63... -
Page 13: Table 5-3 : Register Space
PSI5 Status IRQ Trigger Register 0x428 Interrupt Status Register 0x42C - 0xFE7 Reserved Board Status Registers 0xFF4 Board Health Register 0xFF8 Scratchpad Register 0xFFC Firmware Identification Register Table 5-3 : Register Space TPMC160 User Manual Issue 1.0.2 Page 13 of 63... -
Page 14: Common Protocol Registers
For each of the eight channels the protocol is freely selectable. Protocol options: MODE Description Channel disabled Custom protocol / Manual current setting Square Wave Protocol PWM Protocol AK Protocol / VDA Protocol PSI5 Protocol Others Reserved TPMC160 User Manual Issue 1.0.2 Page 14 of 63... -
Page 15: Current Level Registers 0X004 - 0X020
0x00C Current Level Register Channel 3 0x010 Current Level Register Channel 4 0x014 Current Level Register Channel 5 0x018 Current Level Register Channel 6 0x01C Current Level Register Channel 7 0x020 TPMC160 User Manual Issue 1.0.2 Page 15 of 63... -
Page 16: Adc Data Register Ch0-1 0X024
15:10 Reserved ADC4 Last sampled ADC value of Channel 4 Voltage = ADC4 * 26.16 mV Table 5-8 : ADC Data Register Ch4-5 A new value is provided every 1.6 µs. TPMC160 User Manual Issue 1.0.2 Page 16 of 63... -
Page 17: Adc Data Register Ch6-7 0X030
15:10 Reserved ADC6 Last sampled ADC value of Channel 6 Voltage = ADC6 * 26.16 mV Table 5-9 : ADC Data Register Ch6-7 A new value is provided every 1.6 µs. TPMC160 User Manual Issue 1.0.2 Page 17 of 63... -
Page 18: Custom Protocol Registers
5.3.3 Custom Protocol Registers The TPMC160 supports custom protocols by allowing the manual setting of the current level. This can be done either directly through the CP[x] DEFAULT bits, or as a sequence through the CP FIFO. After starting a sequence, each current level is provided one after the other for a duration of CP[x] TP. As soon as the Manual Sequence FIFO is empty the corresponding output is set to the value defined by the CP[x] DEFAULT bits. - Page 19 0x058 CP Cycle Register Channel 3 0x05C CP Cycle Register Channel 4 0x060 CP Cycle Register Channel 5 0x064 CP Cycle Register Channel 6 0x068 CP Cycle Register Channel 7 0x06C TPMC160 User Manual Issue 1.0.2 Page 19 of 63...
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Page 20: Cp Fifo Status Register 0X070
FIFO full flag of the Custom Protocol FIFO of channel 1 FULL CP FIFO0 FIFO full flag of the Custom Protocol FIFO of channel 0 FULL Table 5-11 : CP FIFO Status Register TPMC160 User Manual Issue 1.0.2 Page 20 of 63... -
Page 21: Cp Fifo Data Registers 0X074 - 0X090
CP FIFO Data Register Channel 3 0x080 CP FIFO Data Register Channel 4 0x084 CP FIFO Data Register Channel 5 0x088 CP FIFO Data Register Channel 6 0x08C CP FIFO Data Register Channel 7 0x090 TPMC160 User Manual Issue 1.0.2 Page 21 of 63... -
Page 22: Square Wave Protocol Registers
1 µs time base 0x3 = 1 ms time base 11:0 SWP[x] Channel [x]: SWP Cycle Time CYCLE The time base depends on the SWP[x] CYCLE BASE. Table 5-13 : SWP Cycle Registers TPMC160 User Manual Issue 1.0.2 Page 22 of 63... - Page 23 0x0B8 SWP Cycle Register Channel 3 0x0BC SWP Cycle Register Channel 4 0x0C0 SWP Cycle Register Channel 5 0x0C4 SWP Cycle Register Channel 6 0x0C8 SWP Cycle Register Channel 7 0x0CC TPMC160 User Manual Issue 1.0.2 Page 23 of 63...
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Page 24: Pwm Protocol Registers
1 µs time base 0x3 = 1 ms time base 11:0 PWM[x] Channel [x]: PWM Protocol Cycle Time CYCLE The time base depends on the PWM[x] CYCLE BASE Table 5-14 : PWM Cycle Registers TPMC160 User Manual Issue 1.0.2 Page 24 of 63... - Page 25 0x128 PWM Cycle Register Channel 3 0x12C PWM Cycle Register Channel 4 0x130 PWM Cycle Register Channel 5 0x134 PWM Cycle Register Channel 6 0x138 PWM Cycle Register Channel 7 0x13C TPMC160 User Manual Issue 1.0.2 Page 25 of 63...
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Page 26: Ak-Protocol / Vda Registers
0x168 AK Cycle Register Channel 3 0x16C AK Cycle Register Channel 4 0x170 AK Cycle Register Channel 5 0x174 AK Cycle Register Channel 6 0x178 AK Cycle Register Channel 7 0x17C TPMC160 User Manual Issue 1.0.2 Page 26 of 63... -
Page 27: Ak Control Registers 0X180 - 0X19C
0x188 AK Control Register Channel 3 0x18C AK Control Register Channel 4 0x190 AK Control Register Channel 5 0x194 AK Control Register Channel 6 0x198 AK Control Register Channel 7 0x19C TPMC160 User Manual Issue 1.0.2 Page 27 of 63... -
Page 28: Psi5 Protocol Registers
0x228 PSI5 Cycle Register Channel 3 0x22C PSI5 Cycle Register Channel 4 0x230 PSI5 Cycle Register Channel 5 0x234 PSI5 Cycle Register Channel 6 0x238 PSI5 Cycle Register Channel 7 0x23C TPMC160 User Manual Issue 1.0.2 Page 28 of 63... -
Page 29: Psi5 Interrupt Status Registers 0X240
SYNC Pulse was detected during the TRIG PSI5 [5] window. SPUR PSI5 [4] This bits are cleared by reading this register. SPUR PSI5 [3] SPUR PSI5 [2] SPUR PSI5 [1] SPUR PSI5 [0] SPUR TPMC160 User Manual Issue 1.0.2 Page 29 of 63... -
Page 30: Table 5-18 : Psi5 Interrupt Status Registers
This bits are cleared by reading this register. RESET PSI5 [4] RESET PSI5 [3] RESET PSI5 [2] RESET PSI5 [1] RESET PSI5 [0] RESET Reserved Reserved Table 5-18 : PSI5 Interrupt Status Registers TPMC160 User Manual Issue 1.0.2 Page 30 of 63... -
Page 31: Psi5 Status Registers 0X244 - 0X260
0x24C PSI5 Status Register Channel 3 0x250 PSI5 Status Register Channel 4 0x254 PSI5 Status Register Channel 5 0x258 PSI5 Status Register Channel 6 0x25C PSI5 Status Register Channel 7 0x260 TPMC160 User Manual Issue 1.0.2 Page 31 of 63... -
Page 32: Psi5 Detection Registers 0X264 - 0X280
0x26C PSI5 Detection Register Channel 3 0x270 PSI5 Detection Register Channel 4 0x274 PSI5 Detection Register Channel 5 0x278 PSI5 Detection Register Channel 6 0x27C PSI5 Detection Register Channel 7 0x280 TPMC160 User Manual Issue 1.0.2 Page 32 of 63... -
Page 33: Psi5 Control Registers 0X284 - 0X2A0
MODE MODE Mode Asynchronous Mode Synchronous Mode without Daisy Chain Synchronous Mode with Daisy Chain Variable Sync pulse mode (PSI5[x]Pulse Mode has to be PWM) Table 5-21 : PSI5 Control Registers TPMC160 User Manual Issue 1.0.2 Page 33 of 63... -
Page 34: Psi5 Default Data Frame Registers 0X2E4 - 0X300
PSI5 Default Data Frame Register Channel 4 0x2F4 PSI5 Default Data Frame Register Channel 5 0x2F8 PSI5 Default Data Frame Register Channel 6 0x2FC PSI5 Default Data Frame Register Channel 7 0x300 TPMC160 User Manual Issue 1.0.2 Page 34 of 63... -
Page 35: Psi5 Data Frame Fifo Registers 0X304 - 0X320
Table 5-23 : PSI5 Data Frame FIFO Registers To support the Sensor to ECU communication, the TPMC160 offers the PSI5 Data Frame FIFO, which can be used instead of the “PSI5 Default Data Frame Register”. The FIFO holds up to 33 Data Frames, which is sufficient to hold Data Frames required for a complete serial data frame. -
Page 36: Psi5 Fifo Status Register 0X324
FIFO full flag of the channel 3 PSI5 Data Frame FIFO FIFO3 FULL PSI5 FIFO full flag of the channel 2 PSI5 Data Frame FIFO FIFO2 FULL PSI5 FIFO full flag of the channel 1 PSI5 Data Frame FIFO FIFO1 FULL TPMC160 User Manual Issue 1.0.2 Page 36 of 63... -
Page 37: Psi5 Sync Data Registers 0X330 - 0X34C
PSI5 SYNC Data Register Channel 3 0x33C PSI5 SYNC Data Register Channel 4 0x340 PSI5 SYNC Data Register Channel 5 0x344 PSI5 SYNC Data Register Channel 6 0x348 PSI5 SYNC Data Register Channel 7 0x34C TPMC160 User Manual Issue 1.0.2 Page 37 of 63... -
Page 38: Cycle Counter Registers
Writing a ‘1’ resets the Cycle Counter value CNT1 Channel 1: Cycle Counter Reset RESET Writing a ‘1’ resets the Cycle Counter value CNT0 Channel 0: Cycle Counter Reset RESET Writing a ‘1’ resets the Cycle Counter value TPMC160 User Manual Issue 1.0.2 Page 38 of 63... - Page 39 MATCH register. Cleared by writing a ‘1’ CNT0 Channel 0: Match Status MATCH 1 = The counters VALUE register was equal to the corresponding STATUS MATCH register. Cleared by writing a ‘1’ TPMC160 User Manual Issue 1.0.2 Page 39 of 63...
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Page 40: Table 5-26 : Cycle Counter Control Register
When set, the timer starts counting up beginning from 0. CNT0 EN Channel 0: Cycle Counter Enable Register When set, the timer starts counting up beginning from 0. Table 5-26 : Cycle Counter Control Register TPMC160 User Manual Issue 1.0.2 Page 40 of 63... -
Page 41: Cycle Counter Match Registers 0X374 - 0X380
CNT7 Channel 7: Match value for the corresponding Cycle Counter MATCH 15:0 CNT6 Channel 6: Match value for the corresponding Cycle Counter MATCH Table 5-30 : Cycle Counter Match Register Ch6-7 TPMC160 User Manual Issue 1.0.2 Page 41 of 63... -
Page 42: Cycle Counter Value Registers 0X384 - 0X390
CNT7 Channel 7: Actual value of the corresponding Cycle Counter VALUE 15:0 CNT6 Channel 6: Actual value of the corresponding Cycle Counter VALUE Table 5-34 : Cycle Counter Value Register Ch6-7 TPMC160 User Manual Issue 1.0.2 Page 42 of 63... -
Page 43: Interrupt Registers
An interrupt will be generated when the PSI5[x] SYNC CNT value PSM3 IE matches the corresponding PSI5[x] SYNC MATCH VALUE. PSM2 IE PSM1 IE PSM0 IE Table 5-35 : Interrupt Enable Register TPMC160 User Manual Issue 1.0.2 Page 43 of 63... -
Page 44: Psi5 Irq Trigger Enable Register 0X424
PR6 TRIG 1 = PSI5[x] RESET triggers the PSI5 Status Interrupt IRQ PR5 TRIG 0 = PSI5[x] RESET trigger is disabled PR4 TRIG PR3 TRIG PR2 TRIG PR1 TRIG PR0 TRIG TPMC160 User Manual Issue 1.0.2 Page 44 of 63... -
Page 45: Table 5-36 : Psi5 Irq Trigger Enable Register
Reset Symbol Description Access Value Reserved Table 5-36 : PSI5 IRQ Trigger Enable Register TPMC160 User Manual Issue 1.0.2 Page 45 of 63... -
Page 46: Interrupt Status Register 0X428
PSI5 SYNC MATCH IRQ Status PSM6 ST This bits are cleared by reading this register PSM5 ST PSM4 ST PSM3 ST PSM2 ST PSM1 ST PSM0 ST Table 5-37 : Interrupt Status Register TPMC160 User Manual Issue 1.0.2 Page 46 of 63... -
Page 47: Board Status
Firmware Identification Register 0xFFC Reset Symbol Description Access Value 31:24 FW_MAJ Firmware Major Version 23:16 FW_MIN Firmware Minor Version 15:8 FW_REV Firmware Revision FW_BLD Firmware Build Count Table 5-40 : Firmware Identification Register TPMC160 User Manual Issue 1.0.2 Page 47 of 63... -
Page 48: Protocol Setup Examples
// After setup, the custom protocol for channel 0 is activated to load it with 5 write_32bit(Channel Control Register, 0x0000_0001) // Channel 0: Default Current is set to HIGH(10 mA) write_32bit (CP Cycle Register Channel 0, 0xC000_0000) // CP Mode has to be 0 TPMC160 User Manual Issue 1.0.2 Page 48 of 63... -
Page 49: Custom Protocol In Fifo Mode - Sequencer
// Load the Frame into the FIFO. BIT 1 = HIGH; BIT 2 = MID; BIT 3 = HIGH, // The remaining 13 bits are LOW write_32bit(CP FIFO Data Register Channel 2, 0x5555_557B) TPMC160 User Manual Issue 1.0.2 Page 49 of 63... -
Page 50: Custom Protocol In Fifo Mode - Manual Triggered
// Channel 2: Set the bit CP Trig to “1” to start the output of the // second frame. All other bits remain unchanged. write_32bit (CP Cycle Register Channel 2, 0x2028_3005) TPMC160 User Manual Issue 1.0.2 Page 50 of 63... -
Page 51: Square Wave Protocol: Software Procedure Example
// After setup, the Square Wave Protocol for channel 0 is activated write_32bit(Channel Control Register, 0x0000_0002) //Change the Square Wave Protocol timing: Cycle time: 2 ms ; High Time = 200 µs write_32bit (SWP Cycle Register Channel 0, 0x20C8_3002) TPMC160 User Manual Issue 1.0.2 Page 51 of 63... -
Page 52: Pwm Protocol: Software Procedure Example
// The Pulse length is increased from 1 TP to 4 TPs: // Cycle time: 1 ms ; standard TP length = 10 µs, TP multiplier = 4 write_32bit (PWM Cycle Register Channel 0, 0x0641_3001) TPMC160 User Manual Issue 1.0.2 Page 52 of 63... -
Page 53: Ak Protocol: Software Procedure Example
// ASP = Normal Speed Pulse // All nine bits are transmitted write_32bit (AK Control Register Channel 0, 0x0000_9323) // After setup, the AK Protocol for channel 0 is activated write_32bit (Channel Control Register, 0x0000_0004) TPMC160 User Manual Issue 1.0.2 Page 53 of 63... -
Page 54: Psi5 Protocol: Software Procedure Example
(PSI5 Data Frame FIFO Register Channel 0, 0x0222_2222) // After the setup the output is started in by activating the PSI5 protocol for // the channel. write_32bit (Channel Control Register, 0x0000_0005) TPMC160 User Manual Issue 1.0.2 Page 54 of 63... -
Page 55: Synchronous Mode
(PSI5 Data Frame FIFO Register Channel 0, 0x0222_2222) // After the setup the output is started in by activating the PSI5 protocol for // the channel. write_32bit (Channel Control Register, 0x0000_0005) TPMC160 User Manual Issue 1.0.2 Page 55 of 63... -
Page 56: Daisy Chain Operation
Wait for the ECU to assign the time slot and set up the PSI5[x] SLOT DELAY. Then Change the PSI5[x] BUS MODE to “Synchronous Mode with Daisy Chain”. The supply voltage is than passed on. Please refer to the PSI5 specification. TPMC160 User Manual Issue 1.0.2 Page 56 of 63... -
Page 57: Functional Description
7 Functional Description I/O Electrical Interface The TPMC160 provides 8 channels of automotive sensor simulation, each with a programmable current sink that sinks current from the sensor’s VDD to GND. Each channel also provides a switchable Daisy-Chain GND. Symbol Signal... -
Page 58: Voltage Monitor
VSS (Sensor GND). VSS_DAISY Leave this signal open when the sensor is not used in a daisy-chain topology, when used in a daisy-chain topology, connect it to the VSS of the next sensor. TPMC160 User Manual Issue 1.0.2 Page 58 of 63... -
Page 59: Supported Protocols
Supported Protocols 7.2.1 Wheel Speed The TPMC160 supports the simulation of the three main variants for Wheel Speed Sensors: Standard 2-level (7/14 mA) wheel speed sensors with “Speed Protocol” or “Duty Cycle” PWM encoded 2-level sensors, with support for airgap warning (LR), assembly position (EL) and direction of rotation (DR-R/L) ... -
Page 60: Ak-Protocol" Or "Vda
Figure 7-3 : AK-Protocol / VDA Diagram 7.2.1.4 Custom Protocol The TPMC160 provides a “Custom Protocol” mode, which can be used to simulate sensors that are not covered by the above descriptions. It supports three current levels, and supports a t based FIFO that can hold up to 16 x 16 (=256) current level settings. -
Page 61: Psi5
The ECU can also use the sync pulses for an ECU to Sensor communication (using the "Tooth Gap" or "Pulse Width" method), to which the sensor can reply using an optional "Serial messaging channel" in the data word. TPMC160 User Manual Issue 1.0.2 Page 61 of 63... -
Page 62: Pin Assignment - I/O Connector
Sensor GND Daisy-Chain GND SS_DAISY Sensor Supply Channel 4 Sensor GND Daisy-Chain GND SS_DAISY Sensor Supply Channel 5 Sensor GND Daisy-Chain GND SS_DAISY Sensor Supply Channel 6 Sensor GND Daisy-Chain GND SS_DAISY TPMC160 User Manual Issue 1.0.2 Page 62 of 63... -
Page 63: Table 8-1 : Pin Assignment Front I/O Connector
Name Description Channel Sensor Supply Channel 7 Sensor GND Daisy-Chain GND SS_DAISY 25-50 n.c. Table 8-1 : Pin Assignment Front I/O Connector TPMC160 User Manual Issue 1.0.2 Page 63 of 63...
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