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Related Manuals for Tews Technologies TPMC851
Summary of Contents for Tews Technologies TPMC851
- Page 1 The Embedded I/O Company TPMC851 Multifunction I/O (16 bit ADC/DAC, TTL I/O, Counter) Version 2.1 User Manual Issue 2.1.0 May 2024 TEWS TECHNOLOGIES GmbH Eggerstedter Weg 14, 25421 Pinneberg, Germany Phone: +49 (0) 4101 4058 0 info@tews.com www.tews.com...
- Page 2 However TEWS Technologies GmbH reserves the right to change the product described in this document at any time without notice. TEWS Technologies GmbH is not liable for any damage arising out of the application or use of the device described herein.
- Page 3 "PCI Base Address 2 for Local Address Space 0" initial value 1.0.9 September 2014 corrected in Table "PCI9030 Header" 2.0.0 User Manual Update for TPMC851 V2.0. September 2022 2.1.0 User Manual Update for TPMC851 V2.1. May 2024 TPMC851 User Manual Issue 2.1.0...
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Page 4: Table Of Contents
INSTALLATION ......................62 7.1 ADC Input Wiring .......................... 62 7.2 DAC Output Wiring ........................63 7.3 TTL Digital I/O Interface ........................ 63 PIN ASSIGNMENT – I/O CONNECTOR ..............64 IMPORTANT NOTES ....................65 TPMC851 User Manual Issue 2.1.0 Page 4 of 65... - Page 5 TABLE 4-1 : PCI CONTROLLER HEADER ....................12 TABLE 4-2 : PCI ADDRESS SPACE OVERVIEW ..................12 TABLE 4-3 : CONFIGURATION EEPROM TPMC851-10R ................13 TABLE 4-4 : PCI CONTROLLER CONFIGURATION REGISTER MAP ............14 TABLE 4-5 : LOCAL REGISTER ADDRESS SPACE ..................16 TABLE 4-6 : ADC CONTROL REGISTER ......................
- Page 6 TABLE 6-6 : INPUT CONTROL MODE EVENTS ................... 59 TABLE 6-7 : GATE MODE ..........................59 TABLE 6-8 : INTERRUPT SOURCES ......................61 TABLE 8-1 : PIN ASSIGNMENT I/O CONNECTOR ..................64 TPMC851 User Manual Issue 2.1.0 Page 6 of 65...
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Page 7: Product Description
1 Product Description The TPMC851 combines 32 single ended / 16 differential channels of 16 bit multiplexed analog input, 8 channels of 16 bit analog output, 16 digital I/O lines and 2 32 bit multi-purpose counters on a standard single-width PMC module. -
Page 8: Figure 1-1 : Block Diagram
The TPMC851 offers 2x 32 bit multi-purpose counters. Each counter includes a 32 bit preload register and a 32 bit compare register. The 32 bit counters can be fed with an internal clock or with an external signal supplied by the digital inputs. -
Page 9: Technical Specification
16 bit Conversion Time 10µs max. Accuracy ±1 LSB @ 25°C with correction Linearity ±2 LSB @ 25°C with correction DAC INL/DNL Error ±4/±3 LSB Capacitive Load Up to 10 000pF TPMC851 User Manual Issue 2.1.0 Page 9 of 65... -
Page 10: Table 2-1 : Technical Specification
If FIT rates are not available, MIL-HDBK-217F and MIL-HDBK-217F Notice 2 formulas are used for FIT rate calculation. Humidity 5 – 95 % non-condensing Weight 75.4 g Table 2-1 : Technical Specification TPMC851 User Manual Issue 2.1.0 Page 10 of 65... -
Page 11: Handling And Operation Instructions
3 Handling and operation Instructions This PMC module is sensitive to static electricity. Packing, unpacking and all other module handling has to be done with appropriate care. TPMC851 User Manual Issue 2.1.0 Page 11 of 65... -
Page 12: Addressing
Space 0x14 Little Local Register Address 2 (0x18) Space 3 (0x1C) Sequencer Data RAM ADC/DAC 4 (0x20) Correction Data ROM 5 (0x24) Not Used Table 4-2 : PCI Address Space Overview TPMC851 User Manual Issue 2.1.0 Page 12 of 65... -
Page 13: Configuration Eeprom
0xFFFF 0xE0 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xF0 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF Table 4-3 : Configuration EEPROM TPMC851-10R Subsystem-ID Value (Offset 0x0C): TPMC851-10R 0x000A TPMC851 User Manual Issue 2.1.0 Page 13 of 65... -
Page 14: Pci Controller Register Space
General Purpose I/O Control 0x026D_B6D2 0x70 Hidden1 Register for Power Management Data Select 0x0000_0000 0x74 Hidden 2 Register for Power Management Data Scale 0x0000_0000 Table 4-4 : PCI Controller Configuration Register Map TPMC851 User Manual Issue 2.1.0 Page 14 of 65... -
Page 15: Local Register Address Space
Counter 1 Command Register 0x0138 – 0x013F Not used 0x0140 Interrupt Control Register 0x0144 – 0x014F Factory use only. Do not Write. 0x0150 CNTPRL_EXT Counter 2 Preload Register 0x0154 CNTCMP_EXT Counter 2 Compare Register TPMC851 User Manual Issue 2.1.0 Page 15 of 65... -
Page 16: Table 4-5 : Local Register Address Space
Counter 2 Status Register 0x0164 CNTCOM_EXT Counter 2 Command Register 0x0168-0x01F0 Reserved 0x01F4 BOARD_TEMP Temperature Register 0x01F8 BOARD_SCRATCH Scratchpad Register 0x01FC BOARD_FIRM Firmware Identification Register Table 4-5 : Local Register Address Space TPMC851 User Manual Issue 2.1.0 Page 16 of 65... -
Page 17: Analog Input Registers
Input Voltage Range ±10V GAIN [1:0] ±5V ±2.5V ±1.25V Single/Differential Mode Control 0 = Single-ended mode SE/DIFF 32 single-ended input channels available 1 = Differential mode 16 differential input channels available TPMC851 User Manual Issue 2.1.0 Page 17 of 65... -
Page 18: Table 4-6 : Adc Control Register
(ADCSTAT). Conversions initiated by the sequencer will have no effect to this register. Reset Symbol Description Access Value Reserved 31:16 Write: don't care Read: always reads as '0' 15:0 Stores the converted 16 bit data value. Table 4-7 : ADC Data Register TPMC851 User Manual Issue 2.1.0 Page 18 of 65... -
Page 19: Table 4-8 : Adc Data Coding
This is based on the chip design of the ADC device. Software should ignore the data of the first two ADC conversions after power-up. The software drivers from TEWS Technologies already include these two dummy conversions. TPMC851 User Manual Issue 2.1.0... -
Page 20: Table 4-9 : Adc Status Register
Register as '0' or wait for a Settling Time Interrupt before the conversion is started. The ADC_BUSY bit in the ADC Status Register indicates if the conversion data in the ADC Data Register is valid (ADC_BUSY bit = '0'). TPMC851 User Manual Issue 2.1.0 Page 20 of 65... -
Page 21: Table 4-10 : Adc Sequencer Control Register
If ADC_OUT in the Line Direction Register LINEDIR is set to ‘1’, the trigger signal for the sequencer is available for external use on Dig I/O Line 0. Do not use the External Signal as Sequencer Trigger Source if ADC_OUT is enabled. This will cause the sequencer to lock. TPMC851 User Manual Issue 2.1.0 Page 21 of 65... -
Page 22: Table 4-11 : Adc Sequencer Status Register
Timer Error Flag Active, IRQ Disabled Active, IRQ Instruction RAM Error Flag Active, IRQ Active, IRQ Active, IRQ Table 4-12 : Error Flag IRQ generation Also see chapter ‘Sequencer Errors’ for details. TPMC851 User Manual Issue 2.1.0 Page 22 of 65... -
Page 23: Table 4-13 : Adc Sequencer Timer Register
If a channel is configured as differential channel, the instruction of the associated channel is ignored (see following chart or chapter ‘Pin Assignment – I/O Connector’ for the associated channels). Within a sequence mixed single-ended and differential modes are possible. TPMC851 User Manual Issue 2.1.0 Page 23 of 65... - Page 24 If a sequence is started with an empty instruction RAM, an I-RAM error is issued. The Sequencer Instruction RAM is accessible only while the sequencer is not running (SEQ_ON = 0). TPMC851 User Manual Issue 2.1.0 Page 24 of 65...
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Page 25: Table 4-15 : Adc Sequencer Instruction Ram Register Positions
Channel 30 N/A (Input for Channel 14) 0x98 Channel 31 N/A (Input for Channel 15) 0x9C Channel 32 N/A (Input for Channel 16) Table 4-15 : ADC Sequencer Instruction RAM Register positions TPMC851 User Manual Issue 2.1.0 Page 25 of 65... -
Page 26: Analog Output Registers
Interrupts are generated only if the Master Interrupt Enable (MIE) is enabled in the Interrupt Control Register ICR. If DAC_OUT in the Line Direction Register LINEDIR is set to ‘1’, the trigger signal for the sequencer is available for external use on Dig I/O Line 1. TPMC851 User Manual Issue 2.1.0 Page 26 of 65... -
Page 27: Table 4-17 : Dac Sequencer Status Register
Sequencer Timer Register when a sequence is started. In sequencer timer mode the start of the next sequence is delayed for: Register Value * 100µs. The time base for the sequencer timer is derived from an on board 40 MHz oscillator. TPMC851 User Manual Issue 2.1.0 Page 27 of 65... -
Page 28: Digital I/O Registers
I/O Line 13 0 = TTL I/O line as Input LINEDIR12 I/O Line 12 1 = TTL I/O line as Output LINEDIR11 I/O Line 11 LINEDIR10 I/O Line 10 LINEDIR9 I/O Line 9 TPMC851 User Manual Issue 2.1.0 Page 28 of 65... -
Page 29: Table 4-21 : Line Direction Register
Line Debounce Time Register LINEDBT. The digital input signal must have duration greater than the programmed debounce duration in order to be recognized as a valid input signal. The disabled I/O lines will not be filtered. TPMC851 User Manual Issue 2.1.0 Page 29 of 65... -
Page 30: Table 4-23 : Line Debounce Time Register
1 = TTL I/O line logic high LINEIN5 I/O Line 5 LINEIN4 I/O Line 4 LINEIN3 I/O Line 3 LINEIN2 I/O Line 2 LINEIN1 I/O Line 1 LINEIN0 I/O Line 0 Table 4-24 : Line Input Register TPMC851 User Manual Issue 2.1.0 Page 30 of 65... -
Page 31: Table 4-25 : Line Output Register
An interrupt will be generated when the input line LINEIENP13 I/O Line 13 changes from 0 to 1. LINEIENP12 I/O Line 12 For pending interrupts and interrupt acknowledge see the Line Interrupt Status Register LINEIST. LINEIENP11 I/O Line 11 TPMC851 User Manual Issue 2.1.0 Page 31 of 65... -
Page 32: Table 4-26 : Line Interrupt Enable Register
I/O Line 9 Write access: LINEISTP8 I/O Line 8 1 : clear pending interrupt request LINEISTP7 I/O Line 7 LINEISTP6 I/O Line 6 LINEISTP5 I/O Line 5 LINEISTP4 I/O Line 4 TPMC851 User Manual Issue 2.1.0 Page 32 of 65... -
Page 33: Table 4-27 : Line Interrupt Status Register
LINEISTP3 I/O Line 3 LINEISTP2 I/O Line 2 LINEISTP1 I/O Line 1 LINEISTP0 I/O Line 0 Table 4-27 : Line Interrupt Status Register TPMC851 User Manual Issue 2.1.0 Page 33 of 65... -
Page 34: Counter 1 Registers
Byte or word accesses on this register are not supported and will fail. 4.3.4.4 Counter 1 Control Register CNTCONT (Offset 0x012C) Reset Symbol Description Access Value Reserved 31:15 Write: don't care Read: always reads as '0' TPMC851 User Manual Issue 2.1.0 Page 34 of 65... - Page 35 The Count Mode determines the behavior of the counter. Count Mode Cycling Counter Divide-by-N Single Cycle See chapter ‘Count Modes’ for details. Internal Clock Prescaler CLKDIV Prescaler Clock frequency 40 MHz CLKDIV 20 MHz 10 MHz 5 MHz TPMC851 User Manual Issue 2.1.0 Page 35 of 65...
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Page 36: Table 4-31 : Counter 1 Control Register
In the 'Direction Count' mode this bit corresponds to the Y- input. Sign The Sign bit is set to '1' when the counter overflows, and set to '0' when the counter underflows. TPMC851 User Manual Issue 2.1.0 Page 36 of 65... -
Page 37: Table 4-32 : Counter 1 Status Register
CNTPRL. This bit is cleared immediately after a write access. Reset Counter RCNT Write ‘1’ to reset the counter. This bit is cleared immediately after a write access. Table 4-33 : Counter 1 Command Register TPMC851 User Manual Issue 2.1.0 Page 37 of 65... -
Page 38: Interrupt Control Register Icr (Offset 0X0140)
The interrupt flags in this register are informational only. All interrupts must be acknowledged in their associated registers. Interrupts are generated only if the Master Interrupt Enable (MIE) is enabled in the Interrupt Control Register ICR. TPMC851 User Manual Issue 2.1.0 Page 38 of 65... -
Page 39: Counter 2 Registers
Data Register Latch is active, the OVFL_EXT bit in Counter 2 Status Register will be set to indicate that data was lost. To avoid data inconsistencies this register is developed for a long word (32 bit) read/write access. Byte or word accesses on this register are not supported and will fail. TPMC851 User Manual Issue 2.1.0 Page 39 of 65... - Page 40 The Count Mode determines the behavior of the counter. Count Mode Cycling Counter SCM_EXT Divide-by-N Single Cycle See chapter ‘Count Modes’ for details. Internal Clock Prescaler CLKDIV Prescaler Clock frequency 40 MHz CLKDIV_EXT 20 MHz 10 MHz 5 MHz TPMC851 User Manual Issue 2.1.0 Page 40 of 65...
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Page 41: Table 4-38 : Counter 2 Control Register
See chapter ‘Input Modes’ for details. Table 4-38 : Counter 2 Control Register Interrupts are generated only if the Master Interrupt Enable (MIE) is enabled in the Interrupt Control Register ICR. TPMC851 User Manual Issue 2.1.0 Page 41 of 65... -
Page 42: Table 4-39 : Counter 2 Status Register
This bit is set to '1' when the counter changes from 0x00000000 to 0xFFFFFFFF. This bit must be reset by writing a '1' to this bit. Table 4-39 : Counter 2 Status Register TPMC851 User Manual Issue 2.1.0 Page 42 of 65... -
Page 43: Board Status Register
4.3.7.3 Firmware Identification Register BOARD_FIRM (Offset 0x01FC) Reset Symbol Description Access Value 31:24 FW_MAJ Firmware Major Version 23:16 FW_MIN Firmware Minor Version 15:8 FW_REV Firmware Revision FW_BLD Firmware Build Count Table 3-43 : Firmware Identification Register TPMC851 User Manual Issue 2.1.0 Page 43 of 65... -
Page 44: Adc Sequencer Data Ram
ERROR 0x0C ADC Offset Gain 8 ERROR 0x0E ADC Gain Gain 8 ERROR 0x10 DAC Channel 1 Offset ERROR 0x12 DAC Channel 1 Gain ERROR 0x14 DAC Channel 2 Offset ERROR TPMC851 User Manual Issue 2.1.0 Page 44 of 65... -
Page 45: Table 4-45 : Adc/Dac Correction Data Rom Address Map
DAC Channel 7 Offset ERROR 0x2A DAC Channel 7 Gain ERROR 0x2C DAC Channel 8 Offset ERROR 0x2E DAC Channel 8 Gain ERROR Table 4-45 : ADC/DAC Correction Data ROM Address Map TPMC851 User Manual Issue 2.1.0 Page 45 of 65... -
Page 46: Configuration Hints
Value of 1 issues a reset to the local logic. The local logic remains in this reset condition until the PCI Host clears the bit. The contents of the PCI Controller Configuration Registers are not reset. TPMC851 User Manual Issue 2.1.0 Page 46 of 65... -
Page 47: Programming Hints
The data correction values are obtained during the factory acceptance test and are stored in the Correction Data ROM. Please use the total 16 bit data register value for the ADC correction formula. The basic formula for correcting any ADC reading for the TPMC851 (bipolar input voltage range) is: ... -
Page 48: Dac Correction Formula
Floating point arithmetic or scaled integer arithmetic must be used to avoid rounding errors in computing above formula. The ADC part of the TPMC851 can operate in two modes: the Manual Mode, with little or none support through automation, and the Sequencer Mode, with large support through automation. -
Page 49: Sequencer Mode
(TIMER_ERROR) is not active. A new external trigger is accepted only after a sequence has completed. An external trigger while the sequencer runs is ignored. The update rate depends on the number of enabled channels: Update Rate = 16µs ∙ number of enabled channels TPMC851 User Manual Issue 2.1.0 Page 49 of 65... -
Page 50: Table 6-1 : Sequencer Errors
If the Sequence Timer Register is set to 0x0000 (Sequencer Continuous Mode) the sequencer ignores the data overflow. The Data Overflow Error Flag is always read as ‘0’ in this mode. TPMC851 User Manual Issue 2.1.0 Page 50 of 65... -
Page 51: Application Examples
When the IRQ after Settling Time is issued, the channel is ready for conversion. Write to the ADC Conversion Start Register ADCCONV and acknowledge the Interrupt in the ADC Status Register ADCSTAT (SETTL_IRQ = '1') TPMC851 User Manual Issue 2.1.0 Page 51 of 65... -
Page 52: Figure 6-2 : Flow: Fastest Conversion Of A Specific Single Channel
Figure 6-2 : Flow: Fastest conversion of a specific single channel Conversion time is approx 1.25µs, as long as neither the channel nor the gain is changed (ADC throughput rate up to 250ksps). TPMC851 User Manual Issue 2.1.0 Page 52 of 65... -
Page 53: Figure 6-3 : Flow: Periodic Conversion Of Multiple Channels
Acknowledge the Interrupt and clear the DATA_AV flag in the ADC Sequencer Status Register ADCSEQSTAT (SEQ_IRQ = '1') and read the Sequencer Data RAM Figure 6-3 : Flow: Periodic conversion of multiple channels TPMC851 User Manual Issue 2.1.0 Page 53 of 65... -
Page 54: Figure 6-4 : Flow: Continuous Conversion Of Multiple Channels
Set the Sequencer Timer Register ADCSEQTIMER to 0x0000 Start the Sequencer in the Sequencer Control Register ADCSEQCONT Read the data from the Sequencer Data RAM as needed. Figure 6-4 : Flow: Continuous conversion of multiple channels TPMC851 User Manual Issue 2.1.0 Page 54 of 65... -
Page 55: Dac Operating Modes
The DAC part of the TPMC851 can operate in two modes – Immediate Update or Simultaneous Update. These modes are configured with the Load Mode Select (LOADSEL) bits in the DAC Control Register DACCONT. LOADSEL[1:0] Load Mode Immediate Update Immediate Update:... -
Page 56: Digital Ttl I/O
Note that some digital inputs are internally used in the other parts of the TPMC851: TTL I/O line 0 as ADC sequencer trigger input/output TTL I/O line 1 as DAC sequencer trigger input/output TTL I/O lines 2,3,5 and 6 as inputs for the counters... -
Page 57: Counter Operating Modes
The general purpose counters of the TPMC851 offer 4 Input Modes, 3 Count Modes and 4 Control Modes. The Input Mode determines the input source for the counters and how the counters interpret these input signals: Input Mode I/O Line 2... -
Page 58: Count Modes
With the exception of the Gate Mode, all modes react on a level change on I/O Lines 4/7. Note that if the digital debounce filter is applied, a change in the input level is only detected when the input line is stable for duration greater than the programmed debounce duration. TPMC851 User Manual Issue 2.1.0 Page 58 of 65... -
Page 59: Table 6-6 : Input Control Mode Events
If the 'Single Cycle' mode is active, the event on I/O Lines 4/7 starts the counters. The counters can also be reset by writing '1' to the Reset Counter (RCNT/RCNT_EXT) bit in the Channel Command Registers. TPMC851 User Manual Issue 2.1.0 Page 59 of 65... -
Page 60: Configuration Examples
U/D Count Cycle Counter Load Mode Enable control mode IRQ Capture a position Input Mode Count Mode Control Mode Additional Configuration U/D Count Cycle Counter Latch Mode Enable control mode IRQ TPMC851 User Manual Issue 2.1.0 Page 60 of 65... -
Page 61: Interrupts
Counter 2 Status Register MIRQ_EXT Counter match interrupt 2 CNTCONT_EXT CNTSTAT_EXT Table 6-8 : Interrupt sources The Interrupt Control Register can give a quick overview which interrupt source caused an interrupt. TPMC851 User Manual Issue 2.1.0 Page 61 of 65... -
Page 62: Installation
7 Installation The TPMC851 provides 32 single-ended or 16 differential multiplexed analog inputs. The desired input channel and the mode (single-ended or differential) are selected by programming the input multiplexer. A software programmable gain amplifier with gain settings of 1, 2, 4 and 8 allows a direct connection of a wide range of sensors and instrumentation. -
Page 63: Dac Output Wiring
Figure 7-2 : DAC Output Wiring In total, 16 TTL I/O lines are available on the standard TPMC851. These I/O lines are utilized with an input and output buffer with a 4.7kΩ pull up resistor for the tri-state output function and an array for ESD protection. See the following figure for more information. -
Page 64: Pin Assignment - I/O Connector
TTL I/O 5 (Counter 2 input) TTL I/O 13 TTL I/O 6 (Counter 2 input) TTL I/O 14 TTL I/O 7 (Counter 2 input) TTL I/O 15 Table 8-1 : Pin Assignment I/O Connector TPMC851 User Manual Issue 2.1.0 Page 64 of 65... -
Page 65: Important Notes
If the sequencer is to be used, these two dummy conversions are absolutely necessary. If a TEWS Technologies software drivers is used, these two dummy conversions are already included. Unused Multiplexer inputs can pick up stray signals which are injected into the device’s substrate. This turns on spurious substrate devices which badly degrade the performance of the whole multiplexer device.
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