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Tews Technologies TPCE636 User Manual

Reconfigurable fpga with 16x 16bit analog input and 16x 16bit analog output
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The Embedded I/O Company
TPCE636
Reconfigurable FPGA with 16x 16bit Analog Input
and 16x 16bit Analog Output
Version 1.0
User Manual
Issue 1.0.2
January 2019
TEWS TECHNOLOGIES GmbH
Am Bahnhof 7
25469 Halstenbek, Germany
Phone: +49 (0) 4101 4058 0
Fax: +49 (0) 4101 4058 19
e-mail:
info@tews.com
www.tews.com

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  • Page 1 Reconfigurable FPGA with 16x 16bit Analog Input and 16x 16bit Analog Output Version 1.0 User Manual Issue 1.0.2 January 2019 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek, Germany Phone: +49 (0) 4101 4058 0 Fax: +49 (0) 4101 4058 19 e-mail: info@tews.com...
  • Page 2 TPCE636-11R in this document at any time without notice. 16x Analog In, 16x Analog Out and 64 direct TEWS TECHNOLOGIES GmbH is not liable for any FPGA Back I/O Lines, damage arising out of the application or use of the XC7K325T-2 FBG676 Kintex-7 FPGA, 1GB device described herein.
  • Page 3 Chapter On-Board Indicators added to the manual. 1.0.1 August 2018 Correction and extension of the JTAG chain description. Correction of the Electrical Interface specification in the 1.0.2 January 2019 Technical Specification table. TPCE636 User Manual Issue 1.0.2 Page 3 of 104...

  • Page 4: Table Of Contents

    ISP Command Register - 0xE8 ....................28 5.2.14 ISP Status Register - 0xEC ....................29 5.2.15 TPCE636 Temperature Sensor Register - 0xF4 ..............30 5.2.16 TPCE636 Serial Number - 0xF8 ..................... 30 5.2.17 BCC - FPGA Code Version - 0xFC ..................31 INTERRUPTS ......................
  • Page 5 9.1.2 Front I/O – Analog Output Level ..................... 77 9.1.3 Back I/O Interface ........................77 10 I/O DESCRIPTION ...................... 78 10.1 Overview ............................78 10.2 Front I/O Connector (X1) ......................79 TPCE636 User Manual Issue 1.0.2 Page 5 of 104...
  • Page 6 FIGURE 10-1 : PIN ASSIGNMENT BACK I/O CONNECTOR TPCE636 ............82 FIGURE 10-2 : FIREFLY BACK I/O CONNECTOR TPCE636 ............... 83 FIGURE 10-3 : PIN ASSIGNMENT FIREFLY BACK I/O CONNECTOR TPCE636 ........83 FIGURE 10-4 : FIREFLY BACK I/O CONNECTOR TPCE636 ............... 84 FIGURE 10-5 : PIN ASSIGNMENT FIREFLY BACK I/O CONNECTOR TPCE636 ........
  • Page 7 TABLE 5-17 : ISP COMMAND REGISTER ..................... 28 TABLE 5-18 : ISP STATUS REGISTER ......................29 TABLE 5-19 : TPCE636 TEMPERATURE SENSOR REGISTER ..............30 TABLE 5-20 : TPCE636 SERIAL NUMBER ....................30 TABLE 5-21: BCC - FPGA CODE VERSION ....................31 TABLE 7-1 : TPCE636 FPGA FEATURE OVERVIEW ...................
  • Page 8 TABLE 7-15: ADC DATA CODING ......................... 60 TABLE 7-16: ADC INTERFACE CONNECTIONS ..................63 TABLE 7-17: TPCE636 PARALLEL DAC INTERFACE ................. 67 TABLE 7-18 : FIREFLY BACK I/O INTERFACE .................... 70 TABLE 7-19: BOARD-STATUS AND USER LEDS ..................73 TABLE 7-20: TPCE636 USER ON-BOARD INDICATORS ................74 TABLE 7-21: USER FPGA RESET INPUTS ....................

  • Page 9: Product Description

    The TPCE636 ADC input channels are based on the Linear Dual 16bit 5Msps Differential LTC2323-16 ADC. The TPCE636 provides 16 ADC channels. Each of the 16 channels has a resolution of 16bit and can work with up to 5Msps. The analog input circuit is designed to allow input voltages of up to ±10V on each input-pin (results in ±20V differential voltage range)

  • Page 10: Technical Specification

    Back I/O Connector male SMC-B 68 (ERNI 154766 64) High Speed Back I/O Connector (Samtec FireFly™) Physical Data Power Requirements Depends on FPGA design With TPCE636 Board Reference Design / without external load typical @ +12V PCIe typical @ +3.3V PCIe TPCE636-xxR 1.3 A not used by TPCE636 TPCE636 User Manual Issue 1.0.2...

  • Page 11: Table 2-1 : Technical Specification

    If FIT rates are not available, MIL-HDBK-217F and MIL-HDBK-217F Notice 2 formulas are used for FIT rate calculation. Humidity 5 – 95 % non-condensing Weight TPCE636-xxR: 208g Table 2-1 : Technical Specification TPCE636 User Manual Issue 1.0.2 Page 11 of 104...

  • Page 12: Handling And Operation Instruction

    3 Handling and Operation Instruction ESD Protection The TPCE636 is sensitive to static electricity. Packing, unpacking and all other handling of the TPCE636 has to be done in an ESD/EOS protected Area. Thermal Considerations Forced air cooling is recommended during operation. Without forced air cooling, damage to the device can occur.

  • Page 13: Pci Device Topology

    4 PCI Device Topology The TPCE636 consists of two FPGAs. Both FPGAs are designed as PCIe / PCI endpoint devices. One FPGA is the User FPGA (Kintex-7) which can be programmed with user defined FPGA code. The second FPGA takes control of on-board hardware functions of TPCE636 and also the configuration control of the User FPGA.

  • Page 14: User Fpga (Kintex-7)

    Table 4-2 : PCI Configuration Registers 4.2.2 PCI BAR Overview Port Size Endian Space Prefetch Width Description (Byte) Mode (Bit) Little Local Configuration Register Space Little In-System Programming Data Space Table 4-3 : PCI BAR Overview TPCE636 User Manual Issue 1.0.2 Page 14 of 104...

  • Page 15: Local Configuration Register Space

    0xC4 Interrupt Status Register 0xC8 Reserved 0xCC Reserved 0xD0 User FPGA Configuration Control/Status Register 0xD4 User FPGA Configuration Data Register (Slave SelectMAP) 0xD8 Reserved 0xDC Reserved 0xE0 ISP Control Register (SPI) TPCE636 User Manual Issue 1.0.2 Page 15 of 104...

  • Page 16: In-System Programming Data Space

    Control and status register for ISP are located in the Local Configuration Register Space. The data register for direct FPGA ISP is also located in the Local Configuration Register Space. TPCE636 User Manual Issue 1.0.2 Page 16 of 104...

  • Page 17: Register Description

    5 Register Description User FPGA (Kintex-7) The FPGA register description depends on the user application and is not part of this specification. TPCE636 User Manual Issue 1.0.2 Page 17 of 104...

  • Page 18: Bcc (Board Configuration Controller) Fpga

    5.2.1 DAC Control / Status Register – 0x00 The output voltage ranges of the TPCE636 DAC outputs are set via DAC Control / Status Register and DAC Output Voltage Range Register. For the three predefined ranges (±10V, ±5V and ±2.5V), the DAC Output Voltage Range Register is set first and then the values are transferred via the DAC Control / Status Register.

  • Page 19: Dac Output Voltage Range Register - 0X04

    10 : ±2.5V range 11 : individual range selection Table 5-2 : DAC Output Voltage Range Register For individual voltage range selection also see the chapter 5.2.3Reference DAC Voltage Control Register. TPCE636 User Manual Issue 1.0.2 Page 19 of 104...

  • Page 20: Reference Dac Voltage Control Register - 0X10 To 0X4C

    5.2.3 Reference DAC Voltage Control Register – 0x10 to 0x4C The 16 TPCE636 DAC outputs consist of eight dual DAC devices (AD5547). Each of these DACs could be used independently. For the generation of the reference voltage of these 16 TPCE636 DACs, two additional serial DAC devices are placed on the TPCE636.

  • Page 21: Table 5-4 : Voltage Coding For The Reference Dac

    Thus, any desired output voltages can be generated. But in any case it is important to ensure that the voltages Vout1 and Vout2 are never set above +10V or below -10V. Voltages above these limits cannot be generated and lead to incorrect outputs. TPCE636 User Manual Issue 1.0.2 Page 21 of 104...

  • Page 22: User Fpga Jtag Control And Status Register - 0X80

    Connector to Kintex-7 is active. USB to JTAG Interface via FTDI2232 is 0b010 connected to Kintex-7. BCC internal JTAG Controller is connected 0b100 to Kintex-7. Table 5-5 : User FPGA JTAG Control and Status Register TPCE636 User Manual Issue 1.0.2 Page 22 of 104...

  • Page 23: User Fpga Jtag Signal Line Register - 0X84

    Reserved JTAG Vector-I/O Enable Controls the state of the BCC JTAG Vector-I/O Interface. JTAG_VIO_EN- 0b0 = Vector-I/O disabled 0b1 = Vector-I/O enabled Functionality is held in reset until enabled is set TPCE636 User Manual Issue 1.0.2 Page 23 of 104...

  • Page 24: User Fpga Jtag Tms Data Register - 0X88

    Sets the JTAG TDI bit data that is shifted-out JTAG_VIO_TDI 31:0 during TMS/TDI shift operations. _DATA Note: Bit 0 is shifted-out first (right-alignment) Table 5-8 : User FPGA JTAG TDI Data Register TPCE636 User Manual Issue 1.0.2 Page 24 of 104...

  • Page 25: User Fpga Jtag Tdo Data Register - 0X90

    0: Interrupt Disabled 1: Interrupt Enabled ISP_DAT_IE While disabled, the corresponding bit in the Interrupt Status Register is ‘0’. Disabling interrupts does not affect the interrupt source. Table 5-11 : Interrupt Enable Register TPCE636 User Manual Issue 1.0.2 Page 25 of 104...

  • Page 26: Interrupt Status Register - 0Xc4

    1: Slave SelectMap (Parallel) FP_CFG_MD After power-up the User FPGA automatically configures from the on-board SPI Flash in ‘Master Serial / SPI’ mode. Table 5-13 : User FPGA Configuration Control/Status Register TPCE636 User Manual Issue 1.0.2 Page 26 of 104...

  • Page 27: User Fpga Configuration Data Register - 0Xd4

    ‘Master Serial / SPI’ mode. Note, that for ISP Direct FPGA Programming, the FPGA must first be set to Slave Select Map configuration mode. Table 5-15 : ISP Control Register TPCE636 User Manual Issue 1.0.2 Page 27 of 104...

  • Page 28: Isp Configuration Register - 0Xe4

    ISP Status Register and starts the configured SPI instruction. ISP_SPI_INS_CMD Ignored (lost) while the Instruction Busy Bit is set in the ISP Status Register. Always read as ‘0’. Table 5-17 : ISP Command Register TPCE636 User Manual Issue 1.0.2 Page 28 of 104...

  • Page 29: Isp Status Register - 0Xec

    (in read mode). Capable of generating an event based interrupt. 0: No ISP SPI Data Transfer in Progress 1: ISP SPI Data Transfer in Progress Table 5-18 : ISP Status Register TPCE636 User Manual Issue 1.0.2 Page 29 of 104...

  • Page 30: Tpce636 Temperature Sensor Register - 0Xf4

    5.2.15 TPCE636 Temperature Sensor Register - 0xF4 Reset Symbol Description Access Value 31:21 Reserved TMP441 Automatic Temperature Read Enable Controls the periodic board temperature read feature. Refresh time = 1s TMP441_AUTO _TRD_EN ‘0’ = disabled ‘1’ = enabled Automatic mode must be disabled before...

  • Page 31: Bcc - Fpga Code Version - 0Xfc

    0x0100_0A00 => bit 23 downto 16 : Minor FPGA Code Version 0x0100_0A00 => bit 15 downto 08 : FPGA Code Revision 0x0100_0A00 => bit 07 downto 00 : FPGA Code Build Number TPCE636 User Manual Issue 1.0.2 Page 31 of 104...

  • Page 32: Interrupts

    The interrupt handling depends on the user application and is not part of this specification. 6.2.2 BCC (Board Configuration Controller) FPGA Both Interrupts of the BCC FPGA must be cleared via writing access to the corresponding Interrupt Status Flag in the Interrupt Status Register. TPCE636 User Manual Issue 1.0.2 Page 32 of 104...

  • Page 33: Functional Description

    - Select Map Bank 115, 116 - SPI Conf. - I2C PCI-Express & P16 MGTs SPI-Flash (FPGA Conf. Data) FIreFly PCIe Switch Back I/O 4 x MGT Figure 7-1 : FPGA Block Diagram TPCE636 User Manual Issue 1.0.2 Page 33 of 104...

  • Page 34: User Fpga Highlights

    XC7K410T 406,720 63.550 1540 1590 28,620 Table 7-1 : TPCE636 FPGA Feature Overview PCI Express Highlights:  Compliant to the PCI Express Base Specification 2.1 with Endpoint and Root Port capability.  Supports Gen1 (2.5 Gb/s) and Gen2 (5 Gb/s)

  • Page 35: User Fpga Gigabit Transceiver (Mgt)

    User FPGA Gigabit Transceiver (MGT) The TPCE636 provides four MGT as Kintex-7 PCI Express Endpoint Block and four MGT for high speed FireFly Back I/O interface. PCIe X4 Interface PCIe X4 Interface Ref. Clock PCIe Clock 100 MHz 156.25 MHz...

  • Page 36: Table 7-4 : Multi Gigabit Transceiver Reference Clocks

    K6 / K5 not connected MGTREFCLK0_116 REFCLK_O2 D6 / D5 100 MHz PI7C9X2G312GP PCIe Switch MGTREFCLK1_116 not used F6 / F5 not connected Table 7-4 : Multi Gigabit Transceiver Reference Clocks TPCE636 User Manual Issue 1.0.2 Page 36 of 104...

  • Page 37: User Fpga Configuration

    At Power-up, the TPCE636 User FPGA (Kintex-7) always configures via x4 SPI Interface by “Master Serial / SPI” mode. At factory default the SPI Flash contains the TEWS example application for the TPCE636 User FPGA device. 7.4.1 Master Serial SPI Flash Configuration It is important for User FPGA Configuration via SPI Master Mode that the ISP Mode Enable (ISP_EN) bit is clear to disable the ISP Mode.

  • Page 38: Manually User Fpga Spi Flash Reconfiguration

    If the PCIe interface of the User FPGA PCIe Endpoint does not change. Device ID, Vendor ID, Class Code and PCI Bars do not change, the PCI header could be saved before the FPGA Reconfiguration and written back to configuration space after the Reconfiguration. TPCE636 User Manual Issue 1.0.2 Page 38 of 104...

  • Page 39: Slave Select Map Configuration

    After reconfiguration was successful the User FPGA Configuration Mode and Set ISP_ENA = 0 the ISP Mode could be disabled. Also the link between the PCIe Switch and Set K7_LINK_ENA = 1 the Kintex-7 must be enabled. TPCE636 User Manual Issue 1.0.2 Page 39 of 104...
  • Page 40 This is also a binary configuration data file but without header information. For configuration of the Kintex-7 FPGA on the TPCE636 both files could be used. Both binary configuration data files have additional data to the actual configuration data.

  • Page 41: Configuration Via Jtag

    7.4.4 Configuration via JTAG The TPCE636 provides two JTAG chains which are accessible by the following connector options: 7.4.4.1 User JTAG Chain For direct FPGA configuration, FPGA read back or in-system diagnostics with Vivado Logic Analyzer, the Molex Debug Connector can be used to access the JTAG-chain. Also an indirect SPI – PROM programming is possible via the User JTAG Chain.

  • Page 42: Programming User Fpga Spi Configuration Flash

    The Programming Instruction always starts at address 0x00 to write data from the ISP Programming Data Space to the SPI flash. If not all configuration data bytes are written, the User FPGA is not configured correctly. TPCE636 User Manual Issue 1.0.2 Page 42 of 104...

  • Page 43: Erasing User Fpga Spi Configuration Flash

    After completion of the erasing process, the ISP Mode bit should be Set FP_CFG_MD = 0 cleared to set configuration path to User FPGA or a User FPGA SPI Set ISP_ENA = 0 Configuration Flash programming process could be done. TPCE636 User Manual Issue 1.0.2 Page 43 of 104...

  • Page 44: Sector Erasing User Fpga Spi Configuration Flash

    After completion of the erasing process, the ISP Mode bit should be Set FP_CFG_MD = 0 cleared to set configuration path to User FPGA or a User FPGA SPI Set ISP_ENA = 0 Configuration Flash programming process could be done. TPCE636 User Manual Issue 1.0.2 Page 44 of 104...

  • Page 45: Reading User Fpga Spi Configuration Flash

    Next Page ? After completion of the reading process, the ISP Mode bit must be cleared Set FP_CFG_MD = 0 to set configuration path back to User FPGA. Set ISP_ENA = 0 TPCE636 User Manual Issue 1.0.2 Page 45 of 104...

  • Page 46: Bcc (Board Configuration Controller) Fpga

    TPCE636 FPGA configuration. 7.5.1 I2C Interface to BCC Register The TPCE636 BCC provides an I2C Interface to the User FPGA (Kintex-7). Via this I2C Interface the TPCE636 Serial Number Register from the BCC Local Configuration Register Space could be read.

  • Page 47: Clocking

    Clocking 7.6.1 FPGA Clock Sources As a central clock generator of the TPCE636 the Si5338 clock generator is used. This provides all necessary clocks for the User FPGA and the Configuration FPGA. The following figure depicts an abstract User FPGA clock flow.

  • Page 48: Table 7-6 : Available Fpga Clocks

    The following table lists the available clock sources on the TPCE636: FPGA Clock Signal Name FPGA Pin Source Description Number CLK_MGT± H6 / H5 SI5338 low-jitter clock 156.25 MHz differential generator MGT Reference clock REFCLKO2± D6 / D5 PCIe Switch...

  • Page 49: Si514 Free Programming Clock Source

    MHz with programming resolution of 0.026 parts per billion. The Si514 on TPCE636 is factory configured to 156 MHz default frequency. The Si514 is connected via I2C interface to User FPGA (Kintex-7). As usual for the I2C interface, the two pins must be realized as open drain buffer.

  • Page 50: Back I/O Interface

    Back I/O Interface The Back I/O Pins of the TPCE636 are directly routed to the User FPGA (Kintex-7). The I/O functions of these FPGA pins are directly dependent on the configuration of the FPGA. The Kintex-7 VCCO voltage is set to 2.5V, so only the 2.5V I/O standards LVCMOS25, LVTTL25 and LVDS_25 are possible when using the TPCE636 back I/O interface.

  • Page 51: Table 7-8 : Digital Back I/O Interface

    BACK_IO28+ IN/OUT LVDS_25 BACK_IO28- IN/OUT LVDS_25 BACK_IO29+ IN/OUT LVDS_25 BACK_IO29- IN/OUT LVDS_25 BACK_IO30+ IN/OUT LVDS_25 BACK_IO30- IN/OUT LVDS_25 BACK_IO31+ IN/OUT LVDS_25 BACK_IO31- IN/OUT LVDS_25 Table 7-8 : Digital Back I/O Interface TPCE636 User Manual Issue 1.0.2 Page 51 of 104...

  • Page 52: Memory

    Memory The TPCE636 is equipped with a 1GB, 32bit wide DDR3 SDRAM and a 128Mbit non-volatile SPI-Flash. The SPI-Flash can also be used as the User FPGA configuration memory. 7.8.1 DDR3 SDRAM The TPCE636 provides two MT41… (96-ball) DDR3 memory devices. The memory is accessible through a Memory Interface Controller Block IP in bank 32, 33 and 34 of the User FPGA.

  • Page 53: Table 7-9 : Ddr3 Sdram Interface

    DQ31 DQ15 CK_p AC13 100Ω CK_n AD13 DQS_0_p AE18 LDQS DQS_0_n AF18 LDQS# DQS_1_p UDQS DQS_1_n UDQS# DQS_2_p LDQS DQS_2_n LDQS# DQS_3_p UDQS DQS_3_n0 UDQS# Table 7-9 : DDR3 SDRAM Interface TPCE636 User Manual Issue 1.0.2 Page 53 of 104...
  • Page 54 Both DDR3 Memory Devices 01 & 02 For details regarding the DDR3 SDRAM interface, please refer to XILINX Memory Interface Generator Documentation. Xilinx UG586: Zynq-7000 AP SoC and 7 Series Devices Memory Interface Solutions v4.0. TPCE636 User Manual Issue 1.0.2 Page 54 of 104...

  • Page 55: Spi-Flash

    7.8.2 SPI-Flash The TPCE636 provides a Cypress S25FL127S 128-Mbit serial Flash memory. This Flash is used as FPGA configuration source (default configuration source). After configuration, it is always accessible from the FPGA, so it also can be used for code or user data storage.

  • Page 56: I2C Calibration Data

    0x03D ADC Channel 16 Offset Low Byte corr 0x03E ADC Channel 16 Gain High Byte corr 0x03F ADC Channel 16 Gain Low Byte corr Table 7-12: ADC Calibration Data Values TPCE636 User Manual Issue 1.0.2 Page 56 of 104...

  • Page 57: Dac Calibration Data Values

    DAC Range ±2.5 Channel 16 Gain 0x0FE High Byte corr DAC Range ±2.5 Channel 16 Gain 0x0FF Low Byte corr 0x100 … not used 0x1FF Table 7-13: DAC Calibration Data Values TPCE636 User Manual Issue 1.0.2 Page 57 of 104...

  • Page 58: Adc Data Correction Formula

    7.8.3.4 ADC Data Correction Formula Please use the total 16 bit data register value for the ADC correction formula. The basic formula for correcting any ADC reading for the TPCE636 (bipolar input voltage range) is:   Gain Offset ...

  • Page 59: Serial Adc Interface

    Serial ADC Interface 7.9.1 Overview The 16 analog inputs of the TPCE636 are realized with 8 LTC2323-16 ADC devices. Each of these SAR- ADCs has two ADC channels. Thus, a total of 16 ADC channels are available on the TPCE636.

  • Page 60: Adc Digital Output Coding

    VIN- and VIN+. An Example: The TPCE636 voltage range is ±10V, so the allowed (single-ended, ground related) voltage on each ADC input pin is ±10V. When we examine the two largest differential voltages, we get following results:...

  • Page 61: User Fpga Pinning

    AA24 ADC_SDO1_02+ 2.5V Differential Data from ADC Channel 4 ADC_SDO1_02- 2.5V ADC_SDO2_02+ 2.5V Differential Data from ADC Channel 5 ADC_SDO2_02- 2.5V Convert Signal for ADC ADC_CNV_N_02 2.5V Channel 4 and 5 TPCE636 User Manual Issue 1.0.2 Page 61 of 104...
  • Page 62 2.5V ADC_SDO1_05+ 2.5V Differential Data from ADC Channel 10 ADC_SDO1_05- 2.5V ADC_SDO2_05+ 2.5V Differential Data from ADC Channel 11 ADC_SDO2_05- 2.5V Convert Signal for ADC ADC_CNV_N_05 2.5V Channel 10 and 11 TPCE636 User Manual Issue 1.0.2 Page 62 of 104...

  • Page 63: Table 7-16: Adc Interface Connections

    Table 7-16: ADC Interface Connections To use the clocked serial interface between the User FPGA (Kintex-7) and one of the eight LTC2323-16 ADC devices please use the LTC2323-16 data sheet which describes the communication process. TPCE636 User Manual Issue 1.0.2 Page 63 of 104...

  • Page 64: Programming Hints Ltc2323-16

    For a detailed description of the LTC2323-16 interface and the LTC2323-16 function please use the data sheet which describes the whole communication process and all special characteristics of the ADC. TPCE636 User Manual Issue 1.0.2 Page 64 of 104...

  • Page 65: Parallel Dac Interface

    Each of these DACs has two DAC channels. Thus, a total of 16 DAC channels are available on the TPCE636. Because of current output DACs it is necessary to use operational amplifier for each DAC output channel to generate an output voltage range up to ±10V.

  • Page 66: User Fpga Pinning

    DAC_LDAC00_01 3.3V Load the DAC output register with contents of the input register. DAC_LDAC02_03 3.3V One write signal for each DAC DAC_LDAC04_05 3.3V device respectively for two DAC DAC_LDAC06_07 3.3V channel. TPCE636 User Manual Issue 1.0.2 Page 66 of 104...

  • Page 67: Table 7-17: Tpce636 Parallel Dac Interface

    Value depends on DAC_MSB line. MSB Power-On Reset State. DAC_MSB = 0 corresponds to zero- DAC_MSB 2.5V scale reset; DAC_MSB = 1 corresponds to midscale reset Table 7-17: TPCE636 parallel DAC Interface TPCE636 User Manual Issue 1.0.2 Page 67 of 104...

  • Page 68: Programming Hints For Ad5547

    7.10.3 Programming Hints for AD5547 TPCE636 DAC Channel write to DAC Input Register Decoding. ADR0 'WR00_01' 'WR02_03' 'WR04_05' 'WR06_07' DAC Channel Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 ADR1 'WR08_09' 'WR10_11'...

  • Page 69: Output Voltage Range

    DAC. 7.10.4 Output Voltage Range The output voltage ranges of the TPCE636 DAC outputs are set via DAC Control / Status Register and DAC Output Voltage Range Register. There are three predefined output voltage ranges ±10V, ±5V, ±2,5V and a fourth mode in which the high and low voltage range can be set individually.

  • Page 70: Digital Interface To Firefly Connector

    Digital Interface to FireFly Connector The digital I/O Pins of the TPCE636 Firefly Back I/O connector are directly routed to the User FPGA (Kintex- 7). The I/O functions of these FPGA pins are directly dependent on the configuration of the FPGA.

  • Page 71: Jtag Controller To K7 Jtag Interface

    TMS/TDI operation. Read-in updates appear immediately on the JTAG Vector-I/O TDO data vector (JTAG_VIO_TDO_DATA). Note that bit #0 is the last one that has been read-in from the JTAG interface. TPCE636 User Manual Issue 1.0.2 Page 71 of 104...

  • Page 72: I2C Bridge

    Channel 4 must be 3.3V SSTL on A and B Do not change Si5338 Core VDD or I2C Bus Voltage Core VDD = 3.3V I2C Bus Voltage = 2.5V or 3.3V TPCE636 User Manual Issue 1.0.2 Page 72 of 104...

  • Page 73: On-Board Indicators

    7.14 On-Board Indicators The TPCE636 provides a couple of board-status LEDs as shown below. These include Power-Good and FPGA configuration status indications as well as two general purpose LEDs. Color State Description On-Board Power Supplies are not ok Power Good...

  • Page 74: User Fpga Pinning

    Signal Bank VCCO Description USER_LED0 3.3V 2x green on-board LEDs USER_LED1 Table 7-20: TPCE636 User On-Board Indicators 7.15 User FPGA Reset Inputs General purpose Reset input connected to the User FPGA Kintex-7. Signal Bank VCCO Description Reset from PCIe Switch...

  • Page 75: Design Help

    8 Design Help Board Reference Design User applications for the TPCE636 may be developed by using the TPCE636 FPGA Board Reference Design. TEWS offers this Board Reference Design as a well-documented basic example. It includes an .xdc constrain file with all necessary pin assignments and basic timing constraints. The example design covers the main functionalities of the TPCE636.

  • Page 76: O Interfaces

    Maximum VIN = ±20.0V Maximum VIN = ±20.0V The TPCE636 has differential analog inputs. When talking about the input voltage range of a differential input, one has to differentiate between the differential input voltage between the two pins, and the input voltage relative to ground for each pin.

  • Page 77: Front I/O - Analog Output Level

    9.1.3 Back I/O Interface All 64 single-ended / 32 differential digital back I/O Pins of the TPCE636 are directly routed from the User FPGA (Kintex-7) to the 68 pin ERNI flat cable connector. The I/O functions of these FPGA pins are directly dependent on the configuration of the FPGA.

  • Page 78: O Description

    10 I/O Description 10.1 Overview TPCE636 User Manual Issue 1.0.2 Page 78 of 104...

  • Page 79: Front I/O Connector (X1)

    Connector View DAC_OUT1 ADC_IN1+ ADC_IN1- DAC_OUT2 ADC_IN2+ ADC_IN2- DAC_OUT3 ADC_IN3+ ADC_IN3- DAC_OUT4 ADC_IN4+ ADC_IN4- ADC_IN5+ DAC_OUT5 ADC_IN5- ADC_IN6+ DAC_OUT6 ADC_IN6- ADC_IN7+ DAC_OUT7 ADC_IN7- ADC_IN8+ DAC_OUT8 ADC_IN8- DAC_OUT9 ADC_IN9+ ADC_IN9- DAC_OUT10 ADC_IN10+ ADC_IN10- TPCE636 User Manual Issue 1.0.2 Page 79 of 104...

  • Page 80: Table 10-2: Pin Assignment Front Panel I/O Connector

    Connector View ADC_IN11+ DAC_OUT11 ADC_IN11- ADC_IN12+ DAC_OUT12 ADC_IN12- ADC_IN13+ DAC_OUT13 ADC_IN13- ADC_IN14+ DAC_OUT14 ADC_IN14- DAC_OUT15 ADC_IN15+ ADC_IN15- DAC_OUT16 ADC_IN16+ ADC_IN16- Table 10-2: Pin Assignment Front Panel I/O Connector TPCE636 User Manual Issue 1.0.2 Page 80 of 104...

  • Page 81: Digital Back I/O Connector (X7)

    BACK_IO12- BACK_IO13+ BACK_IO13- BACK_IO14+ BACK_IO14- BACK_IO15+ BACK_IO15- BACK_IO16+ BACK_IO16- BACK_IO17+ BACK_IO17- BACK_IO18+ BACK_IO18- BACK_IO19+ BACK_IO19- BACK_IO20+ BACK_IO20- BACK_IO21+ BACK_IO21- BACK_IO22+ BACK_IO22- BACK_IO23+ BACK_IO23- BACK_IO24+ BACK_IO24- BACK_IO25+ BACK_IO25- BACK_IO26+ BACK_IO26- BACK_IO27+ BACK_IO27- TPCE636 User Manual Issue 1.0.2 Page 81 of 104...

  • Page 82: Figure 10-1 : Pin Assignment Back I/O Connector Tpce636

    BACK_IO28+ BACK_IO28- BACK_IO29+ BACK_IO29- BACK_IO30+ BACK_IO30- BACK_IO31+ BACK_IO31- Figure 10-1 : Pin Assignment Back I/O Connector TPCE636 TPCE636 User Manual Issue 1.0.2 Page 82 of 104...

  • Page 83: Mgt Back I/O Connector (X8/X9)

    Tx1+ Tx2- Tx3- Tx2+ Tx3+ DIG_IO_0- DIG_IO_1- DIG_IO_0+ DIG_IO_1+ DIG_IO_2+ DIG_IO_3+ DIG_IO_2- DIG_IO_3- Rx3+ Rx2+ Rx3- Rx2- Rx1+ Rx0+ Rx1- Rx0- Figure 10-3 : Pin Assignment Firefly Back I/O Connector TPCE636 TPCE636 User Manual Issue 1.0.2 Page 83 of 104...

  • Page 84: Connector Type

    Samtec – UCC8-010-1-H-S-2-A Figure 10-4 : Firefly Back I/O Connector TPCE636 10.4.4 Pin Assignment UCC8 +3.3V PRESENTL SELECTL INTL RESETL n.c. +3.3V Figure 10-5 : Pin Assignment Firefly Back I/O Connector TPCE636 TPCE636 User Manual Issue 1.0.2 Page 84 of 104...

  • Page 85: Fpga Jtag Header (X5)

    TPCE636 TRST# not connected on the TPCE636 PGND Used on TXMC635 for XILINX Header present detection HALT_INIT_WP signal. Optional. Not connected on the TPCE636 Table 10-4: Pin Assignment JTAG Header TPCE636 User Manual Issue 1.0.2 Page 85 of 104...

  • Page 86: Fpga Usb Connector (X2)

    FPGA USB Connector (X2) 10.6.1 Connector Type Pin-Count Connector Type Würth: USB Typ C, USB 3,1, 24pol. SMT/THT 90° or compatible Source & Order Info 632 723 300 011 Figure 10-7 FPGA USB Connector TPCE636 10.6.2 Pin Assignment Description Description n.c. n.c. n.c.
  • Page 87 PACKAGE_PIN D5 [get_ports REFCLK_02_N] set_property PACKAGE_PIN D6 [get_ports REFCLK_02_P] # Firefly set_property PACKAGE_PIN P2 [get_ports MGTTX0_P] set_property PACKAGE_PIN P1 [get_ports MGTTX0_N] set_property PACKAGE_PIN R4 [get_ports MGTRX0_P] set_property PACKAGE_PIN R3 [get_ports MGTRX0_N] TPCE636 User Manual Issue 1.0.2 Page 87 of 104...
  • Page 88 IOSTANDARD SSTL135_T_DCI [get_ports {DQ[5]}] set_property PACKAGE_PIN AF19 [get_ports {DQ[5]}] set_property SLEW FAST [get_ports {DQ[6]}] set_property IOSTANDARD SSTL135_T_DCI [get_ports {DQ[6]}] set_property PACKAGE_PIN AF20 [get_ports {DQ[6]}] set_property SLEW FAST [get_ports {DQ[7]}] set_property IOSTANDARD SSTL135_T_DCI [get_ports {DQ[7]}] TPCE636 User Manual Issue 1.0.2 Page 88 of 104...
  • Page 89 PACKAGE_PIN V4 [get_ports {DQ[23]}] set_property SLEW FAST [get_ports {DQ[24]}] set_property IOSTANDARD SSTL135_T_DCI [get_ports {DQ[24]}] set_property PACKAGE_PIN Y2 [get_ports {DQ[24]}] set_property SLEW FAST [get_ports {DQ[25]}] set_property IOSTANDARD SSTL135_T_DCI [get_ports {DQ[25]}] set_property PACKAGE_PIN V2 [get_ports {DQ[25]}] TPCE636 User Manual Issue 1.0.2 Page 89 of 104...
  • Page 90 IOSTANDARD SSTL135 [get_ports {A[9]}] set_property PACKAGE_PIN Y7 [get_ports {A[9]}] set_property SLEW FAST [get_ports {A[10]}] set_property IOSTANDARD SSTL135 [get_ports {A[10]}] set_property PACKAGE_PIN Y8 [get_ports {A[10]}] set_property SLEW FAST [get_ports {A[11]}] set_property IOSTANDARD SSTL135 [get_ports {A[11]}] TPCE636 User Manual Issue 1.0.2 Page 90 of 104...
  • Page 91 # DDR3 Chip Select (CS, active-low) set_property SLEW FAST [get_ports {CS_n[0]}] set_property IOSTANDARD SSTL135 [get_ports {CS_n[0]}] set_property PACKAGE_PIN AA13 [get_ports {CS_n[0]}] # DDR3 Data Mask (DM) set_property SLEW FAST [get_ports {DM[0]}] TPCE636 User Manual Issue 1.0.2 Page 91 of 104...
  • Page 92 PACKAGE_PIN AB22 [get_ports {ADC_SCK_P[0]}] set_property IOSTANDARD LVDS_25 [get_ports {ADC_SCKOUT_P[0]}] set_property DIFF_TERM TRUE [get_ports {ADC_SCKOUT_P[0]}] set_property IOSTANDARD LVDS_25 [get_ports {ADC_SCKOUT_N[0]}] set_property DIFF_TERM TRUE [get_ports {ADC_SCKOUT_N[0]}] set_property PACKAGE_PIN AA22 [get_ports {ADC_SCKOUT_N[0]}] set_property PACKAGE_PIN Y22 [get_ports {ADC_SCKOUT_P[0]}] TPCE636 User Manual Issue 1.0.2 Page 92 of 104...
  • Page 93 # External Termination set_property IOSTANDARD LVDS_25 [get_ports {ADC_SCK_N[2]}] # External Termination set_property PACKAGE_PIN V26 [get_ports {ADC_SCK_N[2]}] set_property PACKAGE_PIN U26 [get_ports {ADC_SCK_P[2]}] set_property IOSTANDARD LVDS_25 [get_ports {ADC_SCKOUT_P[2]}] set_property DIFF_TERM TRUE [get_ports {ADC_SCKOUT_P[2]}] TPCE636 User Manual Issue 1.0.2 Page 93 of 104...
  • Page 94 PACKAGE_PIN N16 [get_ports {ADC_CNV_n[4]}] set_property IOSTANDARD LVDS_25 [get_ports {ADC_SCK_P[4]}] # External Termination set_property IOSTANDARD LVDS_25 [get_ports {ADC_SCK_N[4]}] # External Termination set_property PACKAGE_PIN P18 [get_ports {ADC_SCK_N[4]}] set_property PACKAGE_PIN R18 [get_ports {ADC_SCK_P[4]}] TPCE636 User Manual Issue 1.0.2 Page 94 of 104...
  • Page 95 PACKAGE_PIN U19 [get_ports {ADC_SDO2_P[5]}] # ADC #6 set_property SLEW FAST [get_ports {ADC_CNV_n[6]}] set_property IOSTANDARD LVCMOS25 [get_ports {ADC_CNV_n[6]}] set_property PACKAGE_PIN M21 [get_ports {ADC_CNV_n[6]}] set_property IOSTANDARD LVDS_25 [get_ports {ADC_SCK_P[6]}] # External Termination TPCE636 User Manual Issue 1.0.2 Page 95 of 104...
  • Page 96 DIFF_TERM TRUE [get_ports {ADC_SDO2_P[7]}] set_property IOSTANDARD LVDS_25 [get_ports {ADC_SDO2_N[7]}] set_property DIFF_TERM TRUE [get_ports {ADC_SDO2_N[7]}] set_property PACKAGE_PIN P25 [get_ports {ADC_SDO2_N[7]}] set_property PACKAGE_PIN R25 [get_ports {ADC_SDO2_P[7]}] ## ############################################################################################# ## ## Section: DACs (AD5547) ## ############################################################################################# ## TPCE636 User Manual Issue 1.0.2 Page 96 of 104...
  • Page 97 DRIVE 8 [get_ports {DAC_D[12]}] set_property PACKAGE_PIN C18 [get_ports {DAC_D[12]}] set_property IOSTANDARD LVCMOS33 [get_ports {DAC_D[13]}] set_property SLEW SLOW [get_ports {DAC_D[13]}] set_property DRIVE 8 [get_ports {DAC_D[13]}] set_property PACKAGE_PIN B16 [get_ports {DAC_D[13]}] set_property IOSTANDARD LVCMOS33 [get_ports {DAC_D[14]}] TPCE636 User Manual Issue 1.0.2 Page 97 of 104...
  • Page 98 SLEW SLOW [get_ports {DAC_D[27]}] set_property DRIVE 8 [get_ports {DAC_D[27]}] set_property PACKAGE_PIN H16 [get_ports {DAC_D[27]}] set_property IOSTANDARD LVCMOS33 [get_ports {DAC_D[28]}] set_property SLEW SLOW [get_ports {DAC_D[28]}] set_property DRIVE 8 [get_ports {DAC_D[28]}] set_property PACKAGE_PIN G20 [get_ports {DAC_D[28]}] TPCE636 User Manual Issue 1.0.2 Page 98 of 104...
  • Page 99 PACKAGE_PIN H19 [get_ports DAC_WR10_11_N] set_property IOSTANDARD LVCMOS33 [get_ports DAC_WR12_13_N] set_property SLEW SLOW [get_ports DAC_WR12_13_N] set_property DRIVE 8 [get_ports DAC_WR12_13_N] set_property PACKAGE_PIN K16 [get_ports DAC_WR12_13_N] set_property IOSTANDARD LVCMOS33 [get_ports DAC_WR14_15_N] set_property SLEW SLOW [get_ports DAC_WR14_15_N] TPCE636 User Manual Issue 1.0.2 Page 99 of 104...
  • Page 100 IOSTANDARD LVDS_25 [get_ports DIG_IO_01_N] set_property PACKAGE_PIN D10 [get_ports DIG_IO_01_N] set_property IOSTANDARD LVDS_25 [get_ports DIG_IO_02_P] set_property PACKAGE_PIN N19 [get_ports DIG_IO_02_P] set_property IOSTANDARD LVDS_25 [get_ports DIG_IO_02_N] set_property PACKAGE_PIN M20 [get_ports DIG_IO_02_N] set_property IOSTANDARD LVDS_25 [get_ports DIG_IO_03_P] TPCE636 User Manual Issue 1.0.2 Page 100 of 104...
  • Page 101 PACKAGE_PIN H13 [get_ports BACK_IO8_N] set_property IOSTANDARD LVDS_25 [get_ports BACK_IO9_P] set_property PACKAGE_PIN H14 [get_ports BACK_IO9_P] set_property IOSTANDARD LVDS_25 [get_ports BACK_IO9_N] set_property PACKAGE_PIN G14 [get_ports BACK_IO9_N] set_property IOSTANDARD LVDS_25 [get_ports BACK_IO10_P] set_property PACKAGE_PIN J11 [get_ports BACK_IO10_P] TPCE636 User Manual Issue 1.0.2 Page 101 of 104...
  • Page 102 IOSTANDARD LVDS_25 [get_ports BACK_IO21_P] set_property PACKAGE_PIN B15 [get_ports BACK_IO21_P] set_property IOSTANDARD LVDS_25 [get_ports BACK_IO21_N] set_property PACKAGE_PIN A15 [get_ports BACK_IO21_N] set_property IOSTANDARD LVDS_25 [get_ports BACK_IO22_P] set_property PACKAGE_PIN B12 [get_ports BACK_IO22_P] set_property IOSTANDARD LVDS_25 [get_ports BACK_IO22_N] TPCE636 User Manual Issue 1.0.2 Page 102 of 104...
  • Page 103 IOSTANDARD DIFF_SSTL135_DCI [get_ports MCB_CLK_N] set_property PACKAGE_PIN AC11 [get_ports MCB_CLK_N] # REF_CLK set_property IOSTANDARD DIFF_SSTL135_DCI [get_ports REF_CLK_P] set_property PACKAGE_PIN AA10 [get_ports REF_CLK_P] set_property IOSTANDARD DIFF_SSTL135_DCI [get_ports REF_CLK_N] set_property PACKAGE_PIN AB10 [get_ports REF_CLK_N] # USER_CLKA TPCE636 User Manual Issue 1.0.2 Page 103 of 104...
  • Page 104 # LEDs set_property SLEW FAST [get_ports {USER_LED[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {USER_LED[0]}] set_property PACKAGE_PIN J26 [get_ports {USER_LED[0]}] set_property SLEW FAST [get_ports {USER_LED[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {USER_LED[1]}] set_property PACKAGE_PIN E26 [get_ports {USER_LED[1]}] TPCE636 User Manual Issue 1.0.2 Page 104 of 104...

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