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Tews Technologies TPMC467-10R User Manual

4 channel rs232/rs422/rs485 programmable serial interface
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The Embedded I/O Company
4 Channel RS232/RS422/RS485
Programmable Serial Interface
TPMC467
Version 1.0
User Manual
Issue 1.0.4
August 2014
TEWS TECHNOLOGIES GmbH
Am Bahnhof 7
Phone: +49 (0) 4101 4058 0
e-mail:
info@tews.com
25469 Halstenbek, Germany
Fax: +49 (0) 4101 4058 19
www.tews.com

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  • Page 1 The Embedded I/O Company TPMC467 4 Channel RS232/RS422/RS485 Programmable Serial Interface Version 1.0 User Manual Issue 1.0.4 August 2014 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek, Germany Phone: +49 (0) 4101 4058 0 Fax: +49 (0) 4101 4058 19 e-mail: info@tews.com www.tews.com...
  • Page 2 RJ45 I/O pinout in this document at any time without notice. TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or use of the device described herein.
  • Page 3 Issue Description Date First Issue August 2006 New address TEWS LLC September 2006 Technical Specification update January 2007 1.0.3 New notation for HW Engineering Documentation Releases December 2009 1.0.4 General Revision August 2014 TPMC467 User Manual Issue 1.0.4 Page 3 of 30...

  • Page 4: Table Of Contents

    6.1 UART Baud Rate Programming ....................27 PIN ASSIGNMENT – I/O CONNECTOR ..............29 7.1 Front Panel I/O Connector (TPMC467-10R) ................29 7.2 Front Panel I/O Connector (TPMC467-11R) ................29 7.3 Serial Channel to Front Panel Port Mapping ................30 TPMC467 User Manual Issue 1.0.4...
  • Page 5 List of Figures FIGURE 1-1 : BLOCK DIAGRAM ........................6 FIGURE 5-1 : CPLD-BUS BLOCK DIAGRAM ....................18 FIGURE 5-2 : CPLD-BUS WRITE ........................19 FIGURE 5-3 : CPLD-BUS READ ........................20 FIGURE 5-4 : RS422 MULTIDROP CONFIGURATION ................. 23 FIGURE 5-5: RS422 FULL DUPLEX POINT TO POINT CONFIGURATION ..........

  • Page 6: Product Description

    RS232/RS422/RS485 programmable serial interface. The module offers front panel I/O with four RJ45 type connectors. The TPMC467-10R provides a RJ45 I/O pinout according to EIA- 232D. The TPMC467-11R provides a non standard RJ45 I/O pinout (as used on Motorola CPU boards).

  • Page 7: Technical Specification

    ESD Protection ±15kV - Human Body Model I/O Connector 4x RJ45 Modular Jack (AMP 406 732-1) Front I/O Pinout RS232 (TPMC467-10R): Compliant to TIA/EIA-561 (EIA-232D) RS232 (TPMC467-11R): Compliant to TIP866-TM-20 RS422 (TPMC467-11R): Compliant to TIP866-TM-20 Physical Data Power Requirements 40 mA typical @ +5V DC (Shutdown, no load)

  • Page 8: Table 2-1 : Technical Specification

    MTBF TPMC467-10R: 360 000 h TPMC467-11R: 360 000 h MTBF values shown are based on calculation according to MIL-HDBK-217F and MIL-HDBK-217F Notice 2; Environment: G 20°C. The MTBF calculation is based on component FIT rates provided by the component suppliers. If FIT rates are not available, MIL-HDBK-217F and MIL-HDBK-217F Notice 2 formulas are used for FIT rate calculation.

  • Page 9: Local Space Addressing

    3 Local Space Addressing 3.1 XR17D154 Local Space Configuration The local on board addressable regions are accessed from the PCI side by using the XR17D154 local space. XR17D154 PCI Base Size Port Endian Description Address Space Width Mode (Byte) Mapping (Offset in PCI (Bit) Configuration...

  • Page 10: Uart Register Sets

    3.2.1 UART Register Sets The Device Configuration Space provides a register set for each of the 4 UARTs. UART Register Set Register Set Offset Serial Channel 0 0x0000 Serial Channel 1 0x0200 Serial Channel 2 0x0400 Serial Channel 3 0x0600 Table 3-3 : UART Register Set Offset Offset Address Description...

  • Page 11: Device Configuration Registers

    3.2.2 Device Configuration Registers The Device Configuration Registers control general operating conditions and monitor the status of various functions. This includes a 16 bit general purpose counter, multipurpose input/outputs (not supported by the TPMC467), sleep mode, soft-reset and device identification, and revision. They are embedded inside the UART 0 Register Set.

  • Page 12: Uart Channel Configuration Registers

    3.2.3 UART Channel Configuration Registers Each UART channel has its own set of internal UART configuration registers for its own operation control and status reporting. The following table provides the register offsets within a register set, access types and access control: Register Comment Register...
  • Page 13 The address for a UART Channel Configuration Register x in a UART Register Set for channel y PCI Base Address 0 (PCI Base Address for the UART Register Space) + UART Register Set Offset for channel y + Register Offset for register x Addressing example: The address for the LCR register of UART channel 2 is: PCI Base Address...

  • Page 14: Xr17D154 Target Chip

    Max_Lat Min_Gnt Interrupt Pin Interrupt Line Y[7:0] 00 00 01 00 Table 4-1 : PCI Header Device-ID: 0x01D3 TPMC467 Vendor-ID: 0x1498 TEWS TECHNOLOGIES Revision ID: XR17D154 silicon revision Subsystem-ID: 0x000A -10R 0x000B -11R Subsystem Vendor-ID: 0x1498 TEWS TECHNOLOGIES TPMC467 User Manual Issue 1.0.4...

  • Page 15: Configuration Eeprom

    Subsystem ID 0x2C s.b. Table 4-2 : Configuration EEPROM TPMC467-xx Subsystem-ID Value (Offset 0x0C): TPMC467-10R 0x000A TPMC467-11R 0x000B The words following the configuration data contain: • The module version and revision • The UART clock frequency in Hz • The physical interface attached to the serial channels •...

  • Page 16: Table 4-3 : Physical Configuration Eeprom Data

    Address Configuration Register TPMC467-10R TPMC467-11R 0x04 Module Version 0x0100 0x0100 0x05 Module Revision 0x0000 0x0000 0x06 EEPROM Revision 0x0002 0x0002 0x07 Oscillator Frequency (high) 0x02A3 0x02A3 0x08 Oscillator Frequency (low) 0x0000 0x0000 0x09-0x0F Reserved 0x10 RS232 Channels 0x000F 0x000F 0x11...

  • Page 17: Configuration Hints

    5 Configuration Hints The TPMC467 physical interfaces of the serial channels are individually software programmable to various interface configurations. For this purpose a CPLD provides a control register for each interface channel. 5.1 CPLD Description The CPLD provides a Channel Control Register for each of the interface channels. Each of the Channel Control Registers is individually addressable.

  • Page 18: Cpld Access

    Symbol Description Access Reset Value RENA Auto RS485 Receiver Enable When the Auto RTS Control feature of the XR17D154 is used in half duplex configurations, this bit can be used to inhibit the reception of an echo of the own data transmission ‘0’: Normal operation (receiver is always enabled) ‘1’: Inhibit echo reception (receiver is disabled during data transmission)

  • Page 19: Accessing Xr17D154 Mpio-Pins

    5.2.1 Accessing XR17D154 MPIO-Pins The MPIO Registers are accessible at PCI Base Address 0 + Device Configuration Register Offset. Address Register Description Access Reset Offset Value 0x08F MPIOINT MPIO Interrupt Mask 0x00 0x090 MPIOLVL MPIO Level Control 0x00 0x091 MPIO3T MPIO Output Pin Tri-state Control 0x00 0x092...

  • Page 20: Read

    Write_XR17D154(MPIOSEL, 0x80); // Setting up MPIOSEL Write_XR17D154(MPIOLVL, 0x19); // CEN = ‘1’, ADR = "011”, D(6) = ‘0’ Write_XR17D154(MPIOLVL, 0x1D); // CLK = ‘1’ Write_XR17D154(MPIOLVL, 0x01); // CLK = ‘0’, ADR = “000”, D(5) = ‘0’ Write_XR17D154(MPIOLVL, 0x05); // CLK = ‘1’ Write_XR17D154(MPIOLVL, 0x01);...

  • Page 21: Serial Interface Channel Setup

    value |= (Read_XR17D154(MPIOLVL) << 6); // Read D(6) Write_XR17D154(MPIOLVL, 0x07); // CLK = ‘1’ Write_XR17D154(MPIOLVL, 0x03); // CLK = ‘0’ value |= (Read_XR17D154(MPIOLVL) << 5); // Read D(5) Write_XR17D154(MPIOLVL, 0x07); // CLK = ‘1’ Write_XR17D154(MPIOLVL, 0x03); // CLK = ‘0’ value |= (Read_XR17D154(MPIOLVL) <<...

  • Page 22: Slew Rate Limiting

    would indicate a line contention. When the channel is unconnected, this may also be used as a build in self test. 5.3.1.3 Slew Rate Limiting The SLEW LIMIT control is used to select the slew-rate limiting of the RS232 transmitters and the RS485/RS422 drivers.

  • Page 23: Rs485/Rs422 Configuration Examples

    5.4 RS485/RS422 Configuration Examples 5.4.1 RS422 Multidrop RS485 HDPLX RENA RTERM TTERM FCTR[5] * Terminate only if the device is a receiver and the end-point of the bus. Figure 5-4 : RS422 Multidrop Configuration 5.4.2 RS422 Full Duplex Point to Point RS485 HDPLX RENA...

  • Page 24: Rs485 Half Duplex Point To Point

    5.4.4 RS485 Half Duplex Point to Point RS485 HDPLX RENA RTERM TTERM FCTR[5] Figure 5-7: RS485 Half Duplex Point to Point Configuration 5.4.5 RS485 Full Duplex Multi-point Also referred to as “party-line” Master RS485 HDPLX RENA RTERM TTERM FCTR[5] Slave RS485 HDPLX RENA...

  • Page 25: Rs485 Half Duplex Multi-Point

    5.4.6 RS485 Half Duplex Multi-point Also referred to as “party-line” RS485 HDPLX RENA RTERM TTERM FCTR[5] * Terminate only if the device is the end-point of the bus. Figure 5-9: RS485 Half Duplex Multi-Point Configuration 5.5 I/O Electrical Interface 5.5.1 ±15kV ESD Protection The receiver inputs and transmitter outputs are characterized for ±15kV ESD protection using the Human Body Model.

  • Page 26: Termination

    5.5.4 Termination The receive and the transmit line can be terminated with a 120Ω termination resistor. The termination is software selectable. 5.6 Block Diagram XR17D154 MAX3161E Termination RS232 TxD / TxD- / Dx- ≥1 RxD / TxD+ / Dx+ & RTS / RxD- CTS / RxD+ RS485...

  • Page 27: Programming Hints

    6 Programming Hints 6.1 UART Baud Rate Programming Each of the 4 UART channels of the TPMC467 provides a programmable Baud Rate Generator. The clock of the XR17D154 UART can be divided by any divisor from 1 to 2 – 1. The divisor can be programmed by the UART channel DLM (Divisor MSB) and DLL (Divisor LSB) registers.
  • Page 28 These steps should be used to modify the DLM, DLL registers of an UART channel: 1. Write 0x80 to the LCR register of the UART channel (enable access to the DLM, DLL registers). 2. Program the DLM, DLL registers of the UART channel. 3.

  • Page 29: Pin Assignment - I/O Connector

    7 Pin Assignment – I/O Connector The TPMC467 front panel I/O connector is a RJ45 modular jack connector (e.g. AMP# 406 732-1). Figure 7-1 : I/O Connector Pinout 7.1 Front Panel I/O Connector (TPMC467-10R) Signal RS232 Signal RS422 TxD+ +5V Termination Supply...

  • Page 30: Serial Channel To Front Panel Port Mapping

    7.3 Serial Channel to Front Panel Port Mapping The serial channels 0-3 are mapped onto the 4 front panel connectors labeled Port1 – Port4. Serial Channel Front Panel Port Channel 0 Port 1 Channel 1 Port 2 Channel 2 Port 3 Channel 3 Port 4 Table 7-3 : Serial Channel to Front Panel Port Mapping...

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Tpmc467-11r

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