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Tews Technologies TAMC640 User Manual

Virtex-5 amc with fmc slot
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The Embedded I/O Company
TAMC640
Virtex-5 AMC with FMC Slot
Version 1.0
User Manual
Issue 1.0.5
November 2016
TEWS TECHNOLOGIES GmbH
Am Bahnhof 7
25469 Halstenbek, Germany
Phone: +49 (0) 4101 4058 0
Fax: +49 (0) 4101 4058 19
e-mail:
info@tews.com
www.tews.com

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  • Page 1 The Embedded I/O Company TAMC640 Virtex-5 AMC with FMC Slot Version 1.0 User Manual Issue 1.0.5 November 2016 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek, Germany Phone: +49 (0) 4101 4058 0 Fax: +49 (0) 4101 4058 19 e-mail: info@tews.com...
  • Page 2 TAMC640-11R TEWS TECHNOLOGIES GmbH has made any effort to ensure that this manual is accurate and same as TAMC640-10R but Full-Size front panel complete. However TEWS TECHNOLOGIES GmbH TAMC640-12R reserves the right to change the product described in this document at any time without notice.
  • Page 3 Table 6-1 “DIP Switch” in chapter 6.2 “DIP-Switch” Samtec Part Number of the FMC Connector corrected (chapter 9.4) 1.0.5 - Typo corrected in Table 5-2 November 2016 - Typo corrected in Table 9-2 TAMC640 User Manual Issue 1.0.5 Page 3 of 69...

  • Page 4: Table Of Contents

    GTP Reference Clock Generator .................... 34 5.11 JTAG ............................... 35 5.12 Thermal Management ........................36 BOARD CONFIGURATION ..................37 Overview ............................37 DIP-Switch ............................. 37 Battery ............................38 Debug Connector .......................... 38 TAMC640 User Manual Issue 1.0.5 Page 4 of 69...
  • Page 5 Board does not power up ......................51 10.3.2 DONE is always off ......................... 51 10.3.3 INIT LED stays illuminated (red) ..................... 51 11 APPENDIX A ....................... 52 12 APPENDIX B ....................... 58 TAMC640 User Manual Issue 1.0.5 Page 5 of 69...
  • Page 6 FIGURE 1-1 : BLOCK DIAGRAM ........................9 FIGURE 4-1 : TEMP. SENSOR LOCATIONS ....................13 FIGURE 5-1 : TAMC640 FUNCTIONAL BLOCK DIAGRAM ................18 FIGURE 5-2 : AMC INTERFACE DIAGRAM ....................20 FIGURE 5-3 : FMC INTERFACE TO VIRTEX-5 FPGA .................. 21 FIGURE 5-4 : A FMC MODULE ........................
  • Page 7 TABLE 4-6 : MODULE CURRENT REQUIREMENT (W/O FMC) ..............16 TABLE 4-7 : AMC POINT-TO-POINT CONNECTIVITY ................. 17 TABLE 4-8 : CLOCK CONFIGURATION ......................17 TABLE 5-1 : TAMC640 FPGA FEATURE OVERVIEW .................. 19 TABLE 5-2 : FPGA BANK USAGE ........................19 TABLE 5-3: FMC-SUPPLIES .......................... 21 TABLE 5-4 : GENERAL PURPOSE I/O ......................

  • Page 8: Product Description

    AC-coupled LVDS communication with a port speed up to 1.0Gb/sec. For flexible I/O solutions the TAMC640 provides a VITA 57.1 high pin count FMC Module slot, allowing active and passive signal conditioning. All FMC I/O lines are directly connected to the FPGA, which maintains the flexibility of the Select I/O technology of the Virtex-5 FPGA.

  • Page 9: Figure 1-1 : Block Diagram

    Figure 1-1 : Block Diagram TAMC640 User Manual Issue 1.0.5 Page 9 of 69...

  • Page 10: Technical Specification

    FMC high pin count slot according to VITA 57.1 (FPGA Mezzanine Card (FMC) Standard) User Defined Signals 80 differential or 160 single-ended I/O plus 4 differential Clocks Multi-Gigabit-Interfaces 2 gigabit data plus 1 gigabit reference clocks TAMC640 User Manual Issue 1.0.5 Page 10 of 69...

  • Page 11: Table 2-1 : Technical Specification

    If FIT rates are not available, MIL-HDBK-217F and MIL-HDBK-217F Notice 2 formulas are used for FIT rate calculation. Humidity 5 – 95 % non-condensing Weight 190 g Table 2-1 : Technical Specification TAMC640 User Manual Issue 1.0.5 Page 11 of 69...

  • Page 12: Handling And Operation Instruction

    3 Handling and Operation Instruction ESD Protection The TAMC640 is sensitive to static electricity. Packing, unpacking and all other handling of the TAMC640 has to be done in an ESD/EOS protected Area. Thermal Considerations Forced air cooling is recommended during operation. Without forced air cooling, damage to the device will occur.

  • Page 13: Ipmi Support

    4 IPMI Support The TAMC640 provides a Module Management Controller (MMC) that performs health monitoring, hot-swap functionality and Field Replaceable Unit (FRU) information storage. The MMC communicates via an Intelligent Platform Management Interface (IPMI) with its superordinated IPMI controller / shelf manager.

  • Page 14: Fru Information

    The MMC stores the module FRU information in a non-volatile EEPROM. Some of the records are writeable to allow adapting the TAMC640 to user FPGA designs. If records are modified, the user is responsible to set the affected checksums to correct values.

  • Page 15: Board Info Area

    -xx = -10 / -11 / -12 / -13 / -14 / -15 Product version V1.0 Rev. B (see board label) Product serial number determined at manufacturing (see board label) Asset tag = Product serial Number Table 4-5 : Product Info Area TAMC640 User Manual Issue 1.0.5 Page 15 of 69...

  • Page 16: Multi Record Area

    The TAMC640’s Virtex-5 FPGA allows implementing a wide range of interfaces (Serial RapidIO, PCI- Express, Gig.-Eth., XAUI, etc.). The MMC stores a Connectivity Record for each interface that is implemented by the TAMC640. By default, the MMC of the TAMC640 stores the following Connectivity Records: •...

  • Page 17: Clock Configuration

    Table 4-8 : Clock Configuration 4.2.5 Modifying FRU Records Some of the records are writeable to allow adapting the TAMC640 to user FPGA designs. If records are modified, the user is responsible to set the affected checksums to correct values.

  • Page 18: Functional Description

    Platform Platform Flash Flash Figure 5-1 : TAMC640 Functional Block Diagram The FPGA is a Virtex-5 LX50T, LX85T or SX50T FPGA. Each FPGA provides four Gigabit Ethernet MACs, and one Endpoint Blocks for PCI Express. TAMC640 User Manual Issue 1.0.5...

  • Page 19: Table 5-1 : Tamc640 Fpga Feature Overview

    LX85T 82,944 3,888 12 / - SX50T 52,224 4,752 12 / - Table 5-1 : TAMC640 FPGA Feature Overview The FPGA is equipped with 14 I/O banks and 12 Multi-Gigabit Transceivers. I/O Bank Signals Remarks 2.5V Configuration no user I/Os...

  • Page 20: Amc Interface

    FMC Interface Instead of a front I/O Connector, the TAMC640 offers a FPGA Mezzanine Card (FMC) module slot. This allows a wide range of connectors to be used with the TAMC640 and customer specific I/O solutions can be easily applied.

  • Page 21: Figure 5-3 : Fmc Interface To Virtex-5 Fpga

    3.3V Table 5-3: FMC-Supplies Vita 57.1 defines this voltage as 0 -3.3V. On the TAMC640, this is limited to 1.2 – 3.3V, because the FPGA I/O buffer will not work with voltages below 1.2V. Vita 57.1 defines this voltage as 0 -VADJ. On the TAMC640, this is limited to 1.2 –VADJ, because the FPGA I/O buffer will not work with voltages below 1.2V.

  • Page 22: Vadj

    If no FMC is present, the TAMC640 is turned on, with a VADJ set to 1.8V. Memory Interfaces The TAMC640 is equipped with two banks of 128 Mbytes, 16 bit wide DDR2 SDRAM, one bank of 2 Mbytes, 18 bit wide QDR-II SRAM and one 64-Mbit non-volatile SPI-Flash.

  • Page 23: Qdr-Ii Sram

    5.3.2 QDR-II SRAM The TAMC640 provides a total of 2 MByte (18MBit) QDR-II SRAM per default (larger memories are possible). The FPGA has access to one QDR-II SRAM device with 1 Mbit depth at 18 bit data bus width. The TAMC640 uses Burst of 4 QDR-II SRAM to lower address-bus switching speed and simultaneously achieve read and write accesses to independent addresses of the SRAM without any wait cycles.

  • Page 24: Reset

    Xilinx UG086: Xilinx Memory Interface Generator (MIG) User Guide. Reset The MMC generates the reset signal to the TAMC640 payload devices. It is connected to the Board Configuration CPLD (BCC) that vice versa generates the reset signal for the FPGA.

  • Page 25: Gpio

    GPIO The TAMC640 has some general purpose I/O connected to the FPGA and the CPLD. Signal Bank Description USER_SWITCH_CPLD 2.5V Select FPGA configuration source: ON = 0x0 (SPI) OFF = 0x1 (Platform Flash) USER_SWITCH_FPGA 1.8V ON = 0x0, OFF = 0x1 GPIO_FPGA 1.8V...

  • Page 26: Uart

    RS-232 interface. A RS-232 transceiver or USB-UART that can work with 1.8V I/O voltage should connect with these signals. TEWS TA900 provides such an interface. Signal Description Rx_FPGA 1.8V Accessible via debug-connector Tx_FPGA 1.8V Table 5-6 : FPGA UART TAMC640 User Manual Issue 1.0.5 Page 26 of 69...

  • Page 27: Multi-Gigabit Transceiver (Gtps)

    Multi-Gigabit Transceiver (GTPs) The TAMC640 provides 12 GTPs (also referred to as Multi Gigabit Transceivers (MGTs), or RocketIOs): • 10 GTPs are wired to AMC ports 0, 1 (common options region) and 4 -11 (fat pipe region). FPGA hardware resources (e.g. PCI Express Endpoint Block or Gigabit Ethernet MACs) can be used with the GTPs connected to these lanes.

  • Page 28: Configuration

    Configuration The user configurable parts of the TAMC640 are the Virtex-5 FPGA, a Board Configuration CPLD (BCC), two Xilinx Platform Flashes, a SPI-Flash and the Clock Generator device (necessary for the GTP Reference- Clock generation). The FPGA can be configured using either of the following sources: •...

  • Page 29: Fpga Configuration

    See also Xilinx XAPP1020 “Post-Configuration Access to SPI Flash” for more details. 5.9.2 FPGA Configuration As aforementioned, besides direct JTAG configuration, the TAMC640 provides up to three configuration sources: the two Platform Flashes and a SPI-Flash. Configuration from the SPI-Flash is done in the Master SPI configuration mode, whereas configuration from the Platform Flash can be done in Master or Slave Serial as well as in Master or Slave SelectMap mode.

  • Page 30: Table 5-7 : Worst Case Fpga Configuration Times

    (A byte-wide interface is used in this mode.) The following table lists the worst case configuration time of all TAMC640 configuration modes. In all Master Modes, the FPGA drives CCLK with ±50% frequency tolerance. The table below calculates with -50% of the nominal frequency.

  • Page 31: Clock Configuration

    1 = Type 2 receiver inputs (failsafe) Table 5-8 : TCLK Transceiver configuration FCLKA is routed through a Jitter attenuator on the TAMC640. Its configuration is also defined by the BCC. The Jitter attenuator guarantees, that the FCLKA jitter is suitable for the Virtex-5 GTP-Transceiver. The output is always enabled.

  • Page 32: Figure 5-11: Clock Configuration

    The TAMC640 provides the Si5338 as a user programmable GTP reference-clock generator. The generator allows changing the GTP reference-clocks to any specific application needs. The Si5338 is configured at each power-up via the PL-I C bus by the BCC. An I C EEPROM is connected to the BCC as non-volatile clock-configuration-data storage.

  • Page 33: Clocks

    5.10 Clocks The TAMC640 has the following main clock sources: • 100 MHz AMC fabric clock FCLKA. Routed through an ICS874001I-05 PCI Express jitter- attenuator, which feeds the Si5338 that generates up to four clocks of any frequency needed. These clocks are connected to GTP reference clock inputs.

  • Page 34: Gtp Reference Clock Generator

    Table 5-10: Available FPGA clocks 5.10.1 GTP Reference Clock Generator The TAMC640 provides a user programmable Si5338 clock generator. The clock generator allows changing the GTP Reference-Clocks to any specific application needs. AMC FCLKA (lead over the on board Jitter Attenuator) or the on board 50 MHz clock can be used as clock source for the GTP reference clock generation.

  • Page 35: Jtag

    The JTAG-chain is either accessible from the Debug Connector or from the AMC backplane JTAG port. If a debug adapter is connected to the TAMC640, the AMC backplane JTAG port is disabled. To ease the use of the JTAG-chain, it is partitioned into segments. Each segment can be separately held inactive and thereby excluded (“bypassed”) from the chain.

  • Page 36: Thermal Management

    Use the Xilinx XPower Estimator (XPE) or XPower Analyzer to determine the necessary amount of additional cooling requirements as forced air cooling. Forced air cooling is recommended during operation. The TAMC640 has a heatsink mounted on the Virtex-5 FPGA. The heatsink provides a R of app. 6 K/W without air flow, with forced air cooling R will decrease to app.

  • Page 37: Board Configuration

    This chapter describes aspects of board configuration prior to board installation. Overview DIP-Switch Debug Connector Figure 6-1 : Pre-Insertion Board Configuration Overview DIP-Switch The DIP-Switch is located on the bottom side of the TAMC640 and provides the following configuration options. Switch Switch Description Position...

  • Page 38: Battery

    The TAMC640 provides a retainer for a 1225 button/coin cell. This battery is only used to store the encryption key inside the FPGA. To enable the usage of FPGA bitstream encryption, a battery (1225 button/coin cell) has to be populated in the TAMC640 battery retainer: 1.

  • Page 39: Installation

    It is within the responsibility of the user to carefully check whether a specific FMC can be used on a Mid-Size TAMC640. When you are not sure that the available spacing to conductive parts of the FMC is sufficient, it is strongly recommended to use a TAMC640 with Full-Size front panel.

  • Page 40: Amc Module Insertion & Hot-Swap

    Blue LED starts “Short Blink” (Hot Swap Negotiation in progress) b. Blue LED turns “ON” (Module is ready to be extracted) 2. Pull the module handle out completely and extract the AMC module from the slot. TAMC640 User Manual Issue 1.0.5 Page 40 of 69...

  • Page 41: Indicators

    USER Green Refer to chapter “GPIO” Blink Table 8-1 : Front Panel LEDs On board LEDs The TAMC640 provides a couple of board-status LEDs as shown below. These include Power-Good and FPGA configuration status indications. DONE INIT VADJ 0.9V Figure 8-2 : On board LED View TAMC640 User Manual Issue 1.0.5...

  • Page 42: Table 8-2 : Board-Status Leds

    Indicates successful FPGA configuration INIT# FPGA INIT-Pin LED DONE Low : Indicates unsuccessful FPGA configuration DONE High : Readback CRC Error if Readback CRC is enabled Table 8-2 : Board-Status LEDs TAMC640 User Manual Issue 1.0.5 Page 42 of 69...

  • Page 43: O Connectors

    User Guide for SelectIO interface signal standards, slew rate control and current drive strength capabilities. 9.2.1 Differential Signaling As defined in the FMC specification, the TAMC640 expects the AC-coupling for DP signals to be placed on the FMC. TAMC640 User Manual Issue 1.0.5...

  • Page 44: Amc-Connector X4

    AMC port 7 (used for Rx7+ Rx15+ PCIe, SRIO, XAUI,...) AMC Port 15 Connected to Tx7- Tx15- GTP_DUAL_X0Y2 Tx7+ Tx15+ Rx17- Rx17+ AMC Port 17 FCLKA- Tx17- Fabric Clock (100MHz) Tx17+ FCLKA+ TAMC640 User Manual Issue 1.0.5 Page 44 of 69...

  • Page 45: Table 9-1: Pin Assignment Amc Connector X4

    Signal Function Signal Function TCLKB- TCLKC- Differential Clock Differential Clock TCLKB+ TCLKC+ TCLKA- TCLKD- Differential Clock Differential Clock TCLKA+ TCLKD+ Table 9-1: Pin Assignment AMC Connector X4 TAMC640 User Manual Issue 1.0.5 Page 45 of 69...

  • Page 46: Fmc Hpc Connector X2

    FMC HPC Connector X2 The TAMC640 provides a High Pin Count interface. The connector is a Samtec #ASP-134486-01. VREF_B_M2C VREF_A_M2C PG_M2C CLK3_M2C_P PRSNT_M2C_L CLK1_M2C_P CLK3_M2C_N CLK1_M2C_N CLK2_M2C_P CLK0_M2C_P HA00_P_CC CLK2_M2C_N CLK0_M2C_N HA00_N_CC HA03_P LA00_P_CC HA02_P HA03_N LA02_P LA00_N_CC HA04_P HA02_N...

  • Page 47: Table 9-2: Pin Assignment Fmc-Connector X2 Row F-K

    LA09_N LA10_N HA16_N LA13_P HA20_P LA13_N LA14_P HA20_N LA14_N LA17_P_CC HB03_P LA17_N_CC HB03_N LA18_P_CC DP1_C2M_P LA23_P LA18_N_CC DP1_C2M_N HB05_P LA23_N HB05_N LA26_P LA27_P HB09_P LA26_N LA27_N HB09_N HB13_P HB13_N 3P3V AUX TAMC640 User Manual Issue 1.0.5 Page 47 of 69...

  • Page 48: Table 9-3: Pin Assignment Fmc-Connector X2 Row A-E

    HB19_P HB19_N TRST_L HB21_P 3P3V HB21_N 3P3V VADJ 3P3V 3P3V Table 9-3: Pin Assignment FMC-Connector X2 Row A-E TAMC640 User Manual Issue 1.0.5 Page 48 of 69...

  • Page 49: Debug-Connector X1

    Debug-Connector X1 Signal Description JTAG SEL A 1k pullup to 3.3 Volt is located on the TAMC640 3.3V JTAG reference I/O voltage Test Data Output Ground Test Data Input Test Mode Select Input Ground Test Clock Ground UART_RxD FPGA UART Receive Data 1.8V...

  • Page 50: Design Help

    It includes an .ucf file with all necessary pin assignments and basic timing constraints. The example design covers the main functionalities of the TAMC640. It implements a DMA capable PCIe endpoint with interrupt support, register mapping, DDR2 and QDR-II memory access and basic I/O to the FMC slot.

  • Page 51: Troubleshooting

    FPGA configuration. If the BCC is erased by mistake, FPGA configuration will fail. You have to reprogram the BCC for successful FPGA configuration and board operation. The factory default BCC program-file is part of the TAMC640-ED and the TAMC640-FDK. 10.3.3 INIT LED stays illuminated (red)
  • Page 52 ## ############################################################################################# ## # Define IO Standards net "CFG_CLK[?]" iostandard = LVCMOS25; net "SCL_PL" iostandard = LVCMOS25; net "SDA_PL" iostandard = LVCMOS25; net "BATTERY_LOW_n" iostandard = LVCMOS25; net "WC_n" iostandard = LVCMOS25; TAMC640 User Manual Issue 1.0.5 Page 52 of 69...
  • Page 53 "SDA_PL" schmitt_trigger; # For Safty Reason on Control I/O net "SCL_CPLD" open_drain; # Uses open drain due to pin circuit net "SCL_CPLD" schmitt_trigger; # For Safty Reason on Control I/O TAMC640 User Manual Issue 1.0.5 Page 53 of 69...
  • Page 54 ## ############################################################################################# ## # Define IO Standards net "CLK_PF1" iostandard = LVCMOS33; net "CE_PF1_n" iostandard = LVCMOS33; net "REV_SEL?_PF1" iostandard = LVCMOS33; net "CLKOUT_PF1" iostandard = LVCMOS33; net "EN_EXT_SEL_PF1_n" iostandard = LVCMOS33; TAMC640 User Manual Issue 1.0.5 Page 54 of 69...
  • Page 55 "SPI_MOSI" loc = P7; # Bank 2 net "SPI_CS_n" loc = P80; # Bank 2 net "SPI_MISO" loc = P13; # Bank 2 net "SPI_CLK" loc = P6; # Bank 2 TAMC640 User Manual Issue 1.0.5 Page 55 of 69...
  • Page 56 "D_IN" loc = P16; # Bank 1 net "M[0]" loc = P34; # Bank 1 net "M[1]" loc = P18; # Bank 1 net "M[2]" loc = P42; # Bank 1 TAMC640 User Manual Issue 1.0.5 Page 56 of 69...
  • Page 57 "MOSI" pullup; # Recommend in UG191 net "CCLK" pullup; # Ensure Valid Input Level net "DONE" schmitt_trigger; # For Safty Reason on Control I/O net "D_IN" pullup; # Recommend in UG191 TAMC640 User Manual Issue 1.0.5 Page 57 of 69...
  • Page 58 Design Tool : Xilinx ISE Design Suit Embedded 12.4 Simulation Tool : Xilinx ISIM included in Design Tool Description : The file lists all FPGA pins that are connected on the TAMC640 Owner : TEWS TECHNOLOGIES GmbH Am Bahnhof 7 D-25469 Halstenbek Tel.: +49 / (0)4101 / 4058-0...
  • Page 59 # BANK 116, on-board generated by SI5338 net "V_REFCLK_811_P" loc = "Y4"; # BANK 114, aligned to the first 8-lanes [8- net "V_REFCLK_811_N" loc = "Y3"; # BANK 114, on-board generated by SI5338 TAMC640 User Manual Issue 1.0.5 Page 59 of 69...
  • Page 60 "Tx_C_P[15]" loc = "AE22"; # BANK 2 net "Tx_C_N[15]" loc = "AE23"; # BANK 2 net "Rx_C_P[15]" loc = "Y11"; # BANK 18 net "Rx_C_N[15]" loc = "W11"; # BANK 18 TAMC640 User Manual Issue 1.0.5 Page 60 of 69...
  • Page 61 ## ############################################################################################# ## ## Section: FMC LA ## ############################################################################################# ## # Define IO Standards net "LA_?[*]" iostandard = "LVDS_12"; # VADJ # Location Constraints net "LA_P[0]" loc = "AH34"; # BANK 13 TAMC640 User Manual Issue 1.0.5 Page 61 of 69...
  • Page 62 = "D32"; # BANK 11 net "LA_N[32]" loc = "A33"; # BANK 11 net "LA_N[33]" loc = "C33"; # BANK 11 ## ############################################################################################# ## ## Section: FMC HA ## ############################################################################################# ## TAMC640 User Manual Issue 1.0.5 Page 62 of 69...
  • Page 63 = period "HA_CLK" 50 MHz high 50 %; ## ############################################################################################# ## ## Section: FMC HB ## ############################################################################################# ## # Define IO Standards net "HB_?[*]" iostandard = "LVDS_12"; # VCC_B (FMC provided Power Supply) TAMC640 User Manual Issue 1.0.5 Page 63 of 69...
  • Page 64 "TCLKC_Rx" loc = "AG22"; # BANK 4 net "TCLKC_Tx" loc = "AH22"; # BANK 4 net "TCLKD_Rx" loc = "AH12"; # BANK 4 net "TCLKD_Tx" loc = "AG13"; # BANK 4 TAMC640 User Manual Issue 1.0.5 Page 64 of 69...
  • Page 65 "QDR0_A[2]" loc = "E12"; # BANK 20 net "QDR0_A[3]" loc = "G11"; # BANK 20 net "QDR0_A[4]" loc = "K8"; # BANK 20 net "QDR0_A[5]" loc = "L6"; # BANK 20 TAMC640 User Manual Issue 1.0.5 Page 65 of 69...
  • Page 66 "DDR0_DQ[8]" loc = "AD7"; # BANK 18 net "DDR0_DQ[9]" loc = "AB7"; # BANK 18 net "DDR0_DQ[10]" loc = "AD6"; # BANK 18 net "DDR0_DQ[11]" loc = "AC5"; # BANK 18 TAMC640 User Manual Issue 1.0.5 Page 66 of 69...
  • Page 67 = SSTL18_II_DCI; net "DDR1_CS_n[*]" iostandard = SSTL18_II_DCI; net "DDR1_ODT[*]" iostandard = SSTL18_II_DCI; net "DDR1_CKE[*]" iostandard = SSTL18_II; net "DDR1_?DM[*]" iostandard = SSTL18_II_DCI; net "DDR1_?DQS_P[*]" iostandard = DIFF_SSTL18_II_DCI; net "DDR1_?DQS_N[*]" iostandard = DIFF_SSTL18_II_DCI; TAMC640 User Manual Issue 1.0.5 Page 67 of 69...
  • Page 68 # BANK 21 net "DDR1_CK_N[0]" loc = "AK31"; # BANK 21 ## ############################################################################################# ## ## Section: Debug Connector ## ############################################################################################# ## # Define I/O Standards net "RX_FPGA" iostandard = "LVCMOS18"; # 1.8V TAMC640 User Manual Issue 1.0.5 Page 68 of 69...
  • Page 69 # BANK 4 net "SDA_PL_1V8" loc = "AB27"; # BANK 21 net "SCL_PL_1V8" loc = "AC27"; # BANK 21 net "PL_LED2_1V8" loc = "AB10"; # BANK 22 # Additional Constraints net "FPGA_RST_n" pullup; TAMC640 User Manual Issue 1.0.5 Page 69 of 69...

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