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Summary of Contents for Tews Technologies TPMC851
- Page 1 TPMC851 Multifunction I/O (16 bit ADC/DAC, TTL I/O, Counter) Version 1.0 User Manual Issue 1.0.9 September 2014 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek, Germany Phone: +49 (0) 4101 4058 0 Fax: +49 (0) 4101 4058 19 e-mail: info@tews.com...
- Page 2 TEWS TECHNOLOGIES GmbH. Any reproduction without written permission is forbidden. (16 bit ADC/DAC, TTL I/O, Counter) TEWS TECHNOLOGIES GmbH has made any effort to ensure that this manual is accurate and complete. However TEWS TECHNOLOGIES GmbH reserves the right to change the product described in this document at any time without notice.
- Page 3 Corrected DAC Data Register Reset Value to 0x0000 January 2010 1.0.8 General Revision August 2014 1.0.9 "PCI Base Address 2 for Local Address Space 0" initial value September 2014 corrected in Table "PCI9030 Header" TPMC851 User Manual Issue 1.0.9 Page 3 of 65...
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Page 4: Table Of Contents
PCI Configuration Registers (PCR) .....................41 4.1.1 PCI9030 Header .........................41 4.1.2 PCI Base Address Initialization...................42 Local Configuration Register (LCR)....................43 Configuration EEPROM ........................44 Local Software Reset........................44 CONFIGURATION HINTS ..................45 Big / Little Endian..........................45 TPMC851 User Manual Issue 1.0.9 Page 4 of 65... - Page 5 INSTALLATION......................62 ADC Input Wiring ..........................62 DAC Output Wiring ........................63 TTL I/O Interface..........................63 PIN ASSIGNMENT – I/O CONNECTOR ..............64 IMPORTANT NOTES ....................65 Dummy Conversions after Power-up..................65 Open Multiplexer Inputs .......................65 TPMC851 User Manual Issue 1.0.9 Page 5 of 65...
- Page 6 TABLE 3-24: LINE INTERRUPT ENABLE REGISTER ..................31 TABLE 3-25: LINE INTERRUPT STATUS REGISTER ..................32 TABLE 3-26: COUNTER PRELOAD REGISTER ...................33 TABLE 3-27: COUNTER COMPARE REGISTER ..................33 TABLE 3-28: COUNTER DATA REGISTER ....................33 TPMC851 User Manual Issue 1.0.9 Page 6 of 65...
- Page 7 TABLE 4-1 : PCI9030 HEADER ........................41 TABLE 4-2 : PCI9030 PCI BASE ADDRESS USAGE ..................42 TABLE 4-3 : PCI9030 LOCAL CONFIGURATION REGISTER ..............43 TABLE 4-4 : CONFIGURATION EEPROM TPMC851-10R................44 TABLE 5-1 : LOCAL BUS LITTLE/BIG ENDIAN .....................45 TABLE 6-1 : SEQUENCER ERRORS......................50 TABLE 6-2 : DAC LOAD MODES ........................55...
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Page 8: Product Description
1 Product Description The TPMC851 combines 32 single ended / 16 differential channels of 16 bit multiplexed analog input, 8 channels of 16 bit analog output, 16 digital I/O lines and a 32 bit multi-purpose counter on a standard single-width PMC module. -
Page 9: Figure 1-1 : Block Diagram
Additionally the TPMC851 offers a 32 bit multi-purpose counter. The counter includes a 32 bit preload register and a 32 bit compare register. The 32 bit counter can be fed with an internal clock or with an external signal supplied by the digital inputs. The 4 counter input modes determine the interpretation of the input signals. -
Page 10: Technical Specification
16 bit Conversion Time 10μs max. Accuracy ±1 LSB @ 25°C after calibration Linearity ±2 LSB @ 25°C after calibration DAC INL/DNL Error ±4/±3 LSB Capacitive Load Up to 10 000pF TPMC851 User Manual Issue 1.0.9 Page 10 of 65... -
Page 11: Table 2-1 : Technical Specification
If FIT rates are not available, MIL-HDBK-217F and MIL-HDBK-217F Notice 2 formulas are used for FIT rate calculation. Humidity 5 – 95 % non-condensing Weight 82 g Table 2-1 : Technical Specification TPMC851 User Manual Issue 1.0.9 Page 11 of 65... -
Page 12: Local Space Addressing
ADC Sequencer Control Register 0x0014 ADCSEQSTAT ADC Sequencer Status Register 0x0018 ADCSEQTIME ADC Sequencer Timer Register 0x001C Not used 0x0020 – 0x009C ADCSEQIRAM ADC Sequencer Instruction RAM 1-32 0x00A0 – 0x00BF Not used TPMC851 User Manual Issue 1.0.9 Page 12 of 65... -
Page 13: Table 3-3 : Register Address Space
Interrupt Control Register 0x0144 – 0x014F Factory use only. Do not Write. 0x0150 – 0x01FF Not used Table 3-3 : Register Address Space Addresses “Not used” will return 0 when read. TPMC851 User Manual Issue 1.0.9 Page 13 of 65... -
Page 14: Analog Input Registers
Gain Factor Input Voltage Range ±10V ±5V ±2.5V ±1.25V SE/DIFF Single/Differential Mode Control 0 = Single-ended mode 32 single-ended input channels available 1 = Differential mode 16 differential input channels available TPMC851 User Manual Issue 1.0.9 Page 14 of 65... -
Page 15: Table 3-4 : Adc Control Register
Do NOT write to this register while the sequencer is running! A write to this register while the sequencer is running can lead to unpredictable results! Interrupts are generated only if the Master Interrupt Enable (MIE) is enabled in the Interrupt Control Register ICR. TPMC851 User Manual Issue 1.0.9 Page 15 of 65... -
Page 16: Adc Data Register Adcdata (Offset 0X0004)
This is based on the chip design of the ADC device. Software should ignore the data of the first two ADC conversions after power-up. The software drivers from TEWS TECHNOLOGIES already include these two dummy conversions. TPMC851 User Manual Issue 1.0.9... -
Page 17: Adc Status Register Adcstat (Offset 0X0008)
This bit must be read as '0' before the conversion data is read from the DATAREG register. Table 3-7 : ADC Status Register Interrupts are generated only if the Master Interrupt Enable (MIE) is enabled in the Interrupt Control Register ICR. TPMC851 User Manual Issue 1.0.9 Page 17 of 65... -
Page 18: Adc Conversion Start Register Adcconv (Offset 0X000C)
If “Sequencer Mode” is selected (SEQCONT register bit 0 is set to ‘1’) all write accesses to the ADC Conversion Start Register ADCCONV are ignored. Please pay attention to the chapter “Important Notes”. TPMC851 User Manual Issue 1.0.9 Page 18 of 65... -
Page 19: Adc Sequencer Control Register Adcseqcont (Offset 0X0010)
If ADC_OUT in the Line Direction Register LINEDIR is set to ‘1’, the trigger signal for the sequencer is available for external use on Dig I/O Line 0. Do not use the External Signal as Sequencer Trigger Source if ADC_OUT is enabled. This will cause the sequencer to lock. TPMC851 User Manual Issue 1.0.9 Page 19 of 65... -
Page 20: Adc Sequencer Status Register Adcseqstat (Offset 0X0014)
Timer Error Flag Active, IRQ Disabled Active, IRQ Instruction RAM Error Flag Active, IRQ Active, IRQ Active, IRQ Table 3-10: Error Flag IRQ generation Also see chapter ‘Sequencer Errors’ for details. TPMC851 User Manual Issue 1.0.9 Page 20 of 65... -
Page 21: Adc Sequencer Timer Register Adcseqtime (Offset 0X0018)
In this mode the Timer Error Flag (TIMER_ERROR) and the Data Overflow Error Flag (DATA_OVERFLOW_ERROR) are not active and will read as ‘0’. The Data Available Flag (DATA_AV) will be active, but will not produce an interrupt. TPMC851 User Manual Issue 1.0.9 Page 21 of 65... -
Page 22: Adc Sequencer Instruction Ram (Offset 0X0020 - Offset 0X009C)
If a sequence is started with an empty instruction RAM, an I-RAM error is issued. The Sequencer Instruction RAM is accessible only while the sequencer is not running (SEQ_ON = 0). TPMC851 User Manual Issue 1.0.9 Page 22 of 65... -
Page 23: Table 3-13: Adc Sequencer Instruction Ram Register Positions
Channel 30 N/A (Input for Channel 14) 0x98 Channel 31 N/A (Input for Channel 15) 0x9C Channel 32 N/A (Input for Channel 16) Table 3-13: ADC Sequencer Instruction RAM Register positions TPMC851 User Manual Issue 1.0.9 Page 23 of 65... -
Page 24: Analog Output Registers
Interrupts are generated only if the Master Interrupt Enable (MIE) is enabled in the Interrupt Control Register ICR. If DAC_OUT in the Line Direction Register LINEDIR is set to ‘1’, the trigger signal for the sequencer is available for external use on Dig I/O Line 1. TPMC851 User Manual Issue 1.0.9 Page 24 of 65... -
Page 25: Dac Sequencer Status Register Dacseqstat (Offset 0X00C4)
RAM has been updated with data for the next sequence. The bit is cleared by writing a '1'. Table 3-15: DAC Sequencer Status Register TPMC851 User Manual Issue 1.0.9 Page 25 of 65... -
Page 26: Dac Sequencer Timer Register Dacseqtime (Offset 0X00C8)
FSR - 1LSB 9.999695V 0x7FFF Midscale + 1LSB 305.2μV 0x0001 Midscale 0x0000 Midscale – 1LSB -305.2μV 0xFFFF -FSR + 1LSB -9.999695V 0x8001 Full Scale (neg.) -10V 0x8000 Table 3-18: DAC Data Coding TPMC851 User Manual Issue 1.0.9 Page 26 of 65... -
Page 27: Digital I/O Registers
LINEDIR1 I/O Line 1 LINEDIR0 I/O Line 0 Table 3-19: Line Direction Register The reset value of the Line Direction Register is 0x0000. That means all TTL I/O lines are inputs. TPMC851 User Manual Issue 1.0.9 Page 27 of 65... -
Page 28: Line Debounce Enable Register Linedeb (Offset 0X0104)
The Line Debounce Time Register allows to program the debounce duration from 100ns to 6.55ms. Use following formula to calculate the debounce duration: Debounce duration = (Line Debounce Time Value * 100ns) + 100ns The debounce time is common for all 16 inputs. TPMC851 User Manual Issue 1.0.9 Page 28 of 65... -
Page 29: Line Input Register Linein (Offset 0X010C)
1 = TTL I/O line logic high LINEIN5 I/O Line 5 LINEIN4 I/O Line 4 LINEIN3 I/O Line 3 LINEIN2 I/O Line 2 LINEIN1 I/O Line 1 LINEIN0 I/O Line 0 Table 3-22: Line Input Register TPMC851 User Manual Issue 1.0.9 Page 29 of 65... -
Page 30: Line Output Register Lineout (Offset 0X0110)
1 = TTL I/O line logic high LINEOUT5 I/O Line 5 LINEOUT4 I/O Line 4 LINEOUT3 I/O Line 3 LINEOUT2 I/O Line 2 LINEOUT1 I/O Line 1 LINEOUT0 I/O Line 0 Table 3-23: Line Output Register TPMC851 User Manual Issue 1.0.9 Page 30 of 65... -
Page 31: Line Interrupt Enable Register Lineien (Offset 0X0114)
I/O Line 1 LINEIENP0 I/O Line 0 Table 3-24: Line Interrupt Enable Register Interrupts are generated only if the Master Interrupt Enable (MIE) is enabled in the Interrupt Control Register ICR. TPMC851 User Manual Issue 1.0.9 Page 31 of 65... -
Page 32: Line Interrupt Status Register Lineist (Offset 0X0118)
1 : clear pending interrupt request LINEISTP5 I/O Line 5 LINEISTP4 I/O Line 4 LINEISTP3 I/O Line 3 LINEISTP2 I/O Line 2 LINEISTP1 I/O Line 1 LINEISTP0 I/O Line 0 Table 3-25: Line Interrupt Status Register TPMC851 User Manual Issue 1.0.9 Page 32 of 65... -
Page 33: Counter Registers
To avoid data inconsistencies this register is developed for a long word (32 bit) read/write access. Byte or word accesses on this register are not supported and will fail. TPMC851 User Manual Issue 1.0.9 Page 33 of 65... -
Page 34: Counter Control Register Cntcont (Offset 0X012C)
Count Mode Cycling Counter Divide-by-N Single Cycle See chapter ‘Count Modes’ for details. CLKDIV Internal Clock Prescaler CLKDIV Prescaler Clock frequency 40 MHz 20 MHz 10 MHz 5 MHz INPUT Input Mode TPMC851 User Manual Issue 1.0.9 Page 34 of 65... -
Page 35: Table 3-29: Counter Control Register
I/O line 2 & 3 See chapter ‘Input Modes’ for details. Table 3-29: Counter Control Register Interrupts are generated only if the Master Interrupt Enable (MIE) is enabled in the Interrupt Control Register ICR. TPMC851 User Manual Issue 1.0.9 Page 35 of 65... -
Page 36: Counter Status Register Cntstat (Offset 0X0130)
This bit is set to '1' when the counter changes from 0x00000000 to 0xFFFFFFFF. This bit must be reset by writing a '1' to this bit. Table 3-30: Counter Status Register TPMC851 User Manual Issue 1.0.9 Page 36 of 65... -
Page 37: Counter Command Register Cntcom (Offset 0X0134)
Register CNTPRL. This bit is cleared immediately after a write access. RCNT Reset Counter Write ‘1’ to reset the counter. This bit is cleared immediately after a write access. Table 3-31: Counter Command Register TPMC851 User Manual Issue 1.0.9 Page 37 of 65... -
Page 38: Interrupt Control Register Icr (Offset 0X0140)
The interrupt flags in this register are informational only. All interrupts must be acknowledged in their associated registers. Interrupts are generated only if the Master Interrupt Enable (MIE) is enabled in the Interrupt Control Register ICR. TPMC851 User Manual Issue 1.0.9 Page 38 of 65... -
Page 39: Adc Sequencer Data Ram
ERROR 0x0E ADC Gain Gain 8 ERROR 0x10 DAC Channel 1 Offset ERROR 0x12 DAC Channel 1 Gain ERROR 0x14 DAC Channel 2 Offset ERROR 0x16 DAC Channel 2 Gain ERROR TPMC851 User Manual Issue 1.0.9 Page 39 of 65... -
Page 40: Table 3-34: Adc/Dac Calibration Rom Data Space Address Map
DAC Channel 7 Offset ERROR 0x2A DAC Channel 7 Gain ERROR 0x2C DAC Channel 8 Offset ERROR 0x2E DAC Channel 8 Gain ERROR Table 3-34: ADC/DAC Calibration ROM Data Space Address Map TPMC851 User Manual Issue 1.0.9 Page 40 of 65... -
Page 41: Pci9030 Target Chip
HS Nxt Cap. HS Cap. ID Y[23:16] 00 00 00 00 0x4C VPD Address VPD Nxt Cap. VPD Cap. ID Y[31:16] 0000 00 03 0x50 VPD Data 00000000 Table 4-1 : PCI9030 Header TPMC851 User Manual Issue 1.0.9 Page 41 of 65... -
Page 42: Pci Base Address Initialization
PCI9030 Local Space 1 Used 0x20 PCI9030 Local Space 2 Used 0x24 PCI9030 Local Space 3 Not used 0x30 Expansion ROM Not used Table 4-2 : PCI9030 PCI Base Address Usage TPMC851 User Manual Issue 1.0.9 Page 42 of 65... -
Page 43: Local Configuration Register (Lcr)
General Purpose I/O Control 0x026D_B6DB No GPIO 0x70 Hidden1 Power Management data select 0x0000_0000 Not used 0x74 Hidden 2 Power Management data scale 0x0000_0000 Not used Table 4-3 : PCI9030 Local Configuration Register TPMC851 User Manual Issue 1.0.9 Page 43 of 65... -
Page 44: Configuration Eeprom
0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF Table 4-4 : Configuration EEPROM TPMC851-10R Subsystem-ID Value (Offset 0x0C): TPMC851-10R 0x000A Local Software Reset The PCI9030 Local Reset Output LRESETo# is used to reset the on board local logic. The PCI9030 local reset is active during PCI reset or if the PCI Adapter Software Reset bit is set in the PCI9030 local configuration register CNTRL (offset 0x50). -
Page 45: Configuration Hints
Byte 0 D[15..8] Byte 1 D[7..0] 8 Bit upper lane 8 Bit Byte 0 D[31..24] Byte 0 D[7..0] 8 Bit lower lane Byte 0 D[7..0] Table 5-1 : Local Bus Little/Big Endian TPMC851 User Manual Issue 1.0.9 Page 45 of 65... - Page 46 Standard use of the TPMC851: Local Address Space 0 32 bit bus in Big Endian Mode Local Address Space 1 16 bit bus in Big Endian Mode Local Address Space 2 16 bit bus in Big Endian Mode Local Address Space 3 not used Expansion ROM Space not used To change the Endian Mode use the Local Configuration Registers for the corresponding Space.
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Page 47: Programming Hints
The data correction values are obtained during factory calibration and are stored in the Calibration Data ROM. 6.1.1 ADC Correction Formula Please use the total 16 bit data register value for the ADC correction formula. The basic formula for correcting any ADC reading for the TPMC851 (bipolar input voltage range) is: Gain Offset corr... -
Page 48: Dac Correction Formula
Floating point arithmetic or scaled integer arithmetic must be used to avoid rounding errors in computing above formula. ADC Operating Modes The ADC part of the TPMC851 can operate in two modes: the Manual Mode, with little or none support through automation, and the Sequencer Mode, with large support through automation. Manual Mode In this mode, the converter operation relies on the user. -
Page 49: Sequencer Mode
(TIMER_ERROR) is not active. A new external trigger is accepted only after a sequence has completed. An external trigger while the sequencer runs is ignored. The update rate depends on the number of enabled channels: Update Rate = 16μs number of enabled channels TPMC851 User Manual Issue 1.0.9 Page 49 of 65... -
Page 50: Sequencer Errors
If the Sequence Timer Register is set to 0x0000 (Sequencer Continuous Mode) the sequencer ignores the data overflow. The Data Overflow Error Flag is always read as ‘0’ in this mode. TPMC851 User Manual Issue 1.0.9 Page 50 of 65... -
Page 51: Application Examples
When the IRQ after Settling Time is issued, the channel is ready for conversion. Write to the ADC Conversion Start Register ADCCONV and acknowledge the Interrupt in the ADC Status Register ADCSTAT (SETTL_IRQ = '1') TPMC851 User Manual Issue 1.0.9 Page 51 of 65... -
Page 52: Figure 6-2 : Flow: Fastest Conversion Of A Specific Single Channel
Interrupt in the ADC Status Register ADCSTAT (ADC_IRQ = '1') and read ADCDATA. Figure 6-2 : Flow: Fastest conversion of a specific single channel Conversion time is approx 1.25μs, as long as neither the channel nor the gain is changed. TPMC851 User Manual Issue 1.0.9 Page 52 of 65... -
Page 53: Periodic Conversion Of Multiple Channels
Acknowledge the Interrupt and clear the DATA_AV flag in the ADC Sequencer Status Register ADCSEQSTAT (SEQ_IRQ = '1') and read the Sequencer Data RAM Figure 6-3 : Flow: Periodic conversion of multiple channels TPMC851 User Manual Issue 1.0.9 Page 53 of 65... -
Page 54: Continuous Conversion Of Multiple Channels
Set the Sequencer Timer Register ADCSEQTIMER to 0x0000 Start the Sequencer in the Sequencer Control Register ADCSEQCONT Read the data from the Sequencer Data RAM as needed. Figure 6-4 : Flow: Continuous conversion of multiple channels TPMC851 User Manual Issue 1.0.9 Page 54 of 65... -
Page 55: Dac Operating Modes
DAC Operating Modes The DAC part of the TPMC851 can operate in two modes – Immediate Update or Simultaneous Update. These modes are configured with the Load Mode Select (LOADSEL) bits in the DAC Control Register DACCONT. LOADSEL[1:0] Load Mode... -
Page 56: Digital Ttl I/O
Digital TTL I/O Note that some digital inputs are internally used in the other parts of the TPMC851: TTL I/O line 0 as ADC sequencer trigger TTL I/O line 1 as DAC sequencer trigger TTL I/O line 2 and TTL I/O line 3 as counter inputs... -
Page 57: Counter Operating Modes
Counter Operating Modes The general purpose counter of the TPMC851 offers 3 Input Modes, 2 Count Modes and 4 Control Modes. 6.5.1 Input Modes The Input Mode determines the input source for the counter and how the counter interprets these input signals:... -
Page 58: Quadrature Count
With the exception of the Gate Mode, all modes react on a level change on the I/O Line 4. Note that if the digital debounce filter is applied, a change in the input level is only detected when the input line is stable for duration greater than the programmed debounce duration. TPMC851 User Manual Issue 1.0.9 Page 58 of 65... -
Page 59: No Control Mode
The watchdog timer counts down from a programmed value until it reaches 0. The counter must be reloaded on a regular base either internal via the Counter Command Register or external via I/O Line 4. Failure to cause a reload would generate a timeout and an interrupt. TPMC851 User Manual Issue 1.0.9 Page 59 of 65... -
Page 60: Event Counting
All Interrupts are requested at the LINT1 input of the PCI9030 Target Chip. Interrupts are generated only if the Master Interrupt Enable (MIE) is enabled in the Interrupt Control Register ICR. 6.6.1 Interrupt Sources IRQ Description Enable IRQ Acknowledge IRQ TPMC851 User Manual Issue 1.0.9 Page 60 of 65... -
Page 61: Table 6-8 : Interrupt Sources
Counter match interrupt Counter Control Register Counter Status Register CNTCONT CNTSTAT Table 6-8 : Interrupt sources The Interrupt Control Register can give a quick overview which interrupt source caused an interrupt. TPMC851 User Manual Issue 1.0.9 Page 61 of 65... -
Page 62: Installation
7 Installation ADC Input Wiring The TPMC851 provides 32 single-ended or 16 differential multiplexed analog inputs. The desired input channel and the mode (single-ended or differential) are selected by programming the input multiplexer. A software programmable gain amplifier with gain settings of 1, 2, 4 and 8 allows a direct connection of a wide range of sensors and instrumentation. -
Page 63: Dac Output Wiring
(open) digital I/O line will be read as ‘1’. A digital I/O line configured as input will appear as a high state to the outside, as long it is not driven from the outside. TPMC851 User Manual Issue 1.0.9 Page 63 of 65... -
Page 64: Pin Assignment - I/O Connector
TTL I/O 4 (Counter input) TTL I/O 12 TTL I/O 5 TTL I/O 13 TTL I/O 6 TTL I/O 14 TTL I/O 7 TTL I/O 15 Table 8-1 : Pin Assignment I/O Connector TPMC851 User Manual Issue 1.0.9 Page 64 of 65... -
Page 65: Important Notes
Use the ADC Conversion Start Register (ADCCONV) Register to perform the dummy conversions. If the sequencer is to be used, these two dummy conversions are absolutely necessary. If one of TEWS TECHNOLOGIES software drivers is used, these two dummy conversions are already included. Open Multiplexer Inputs Unused Multiplexer inputs can pick up stray signals which are injected into the device’s substrate.
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