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5
M M D[31:0]
M MD0
M MD1
M MD2
M MD3
M MD4
M MD5
M MD6
Signal Groupings of DDR-SDRAM:
M MD7
1. Clocks:
M MD8
Differential Pairs:
M MD9
M MD10
D
MCK/MCKn,
M MD11
RMCK0/RMCK0n,
M MD12
M MD13
RMCK1/RMCK1n,
M MD14
MCKFB/MCKFBn
M MD15
M MD16
M MD17
(length mismatch <150mils)
M MD18
- MCK+RMCK0 and MCKn+RMCK0n
M MD19
M MD20
- MCK+RMCK1 and MCKn+RMCK1n
M MD21
- MCK and MCKFBK
M MD22
M MD23
- MCK and MCKFBKn
M MD24
M MD25
2. Data: (length mismatch: <250mils)
M MD26
M MD27
- data bus: MDQ[0..31]+RMDQ[0..31]
M MD28
- data mask: MDM[0..3]+RMDM[0..3]
M MD29
M MD30
- data strobe: MDQS[0..3]+RMDQS[0..3]
M MD31
3. Adress/Command:
- adress bus: MA[0..12]
- bank address: MBNK[0..1]
- row adress strobe: MRCAn
- column adress strobe: MCASn
C
- write enable: MWEn
4. Control:
- clock enable: MCKEn
- chip select: MCSn
- row address strobe: RASn
5. VREF: 10 mils wide
RN1 9
RN2 0
RN2 1
22
22
B
22
RM D QS2
M DQS2
1
8
RM D QS3
M DQS3
2
7
M MD24
M D24
3
6
M MD25
M D25
4
5
RN2 9
22
RM DM2
1
8
M DM2
RM DM3
M DM3
2
7
M MD26
3
6
M D26
M MD27
M D27
4
5
RN3 0
22
RN3 1
M MD28
M D28
1
8
M MD29
M D29
2
7
M MD30
M D30
3
6
M MD31
M D31
4
5
RN3 2
22
22
R MA4
MA4
4
5
A
R MA10
MA10
3
6
RM RASn
2
7
M RASn
RM CASn
M CASn
1
8
R MA5
MA5
1
8
RM CLKE
2
7
M CLKE
RM CSn
M CSn
3
6
RM WEn
4
5
M WEn
RN3 3
22
5
4
U1 5F
M D0
T20
M22
MD0
MREFIN0
M D1
T21
C22
MD1
MREFIN1
M D2
T22
MD2
M D3
R19
MD3
M D4
R20
V22
MD4
MCK
M D5
R21
U21
MD5
MCKN
M D6
R22
U20
MD6
MCKFBK
M D7
P19
T19
MD7
MCKFBKN
M D8
L22
A18
MD8
MCKE
M D9
N20
MD9
M D10
M19
B20
MD10
MRAS
M D11
K22
A19
MD11
MCAS
M D12
M20
A17
MD12
MWE
M D13
M21
B18
MD13
MCS
M D14
L21
MD14
M D15
K21
N22
MD15
MDM0
M D16
H20
N21
MD16
MDM1
M D17
F21
P21
MD17
MDQS0
M D18
D22
P22
MD18
MDQS1
M D19
H19
MD19
M D20
Main
G20
MD20
M D21
E21
Memory
G22
MD21
MA0
M D22
D21
Port
L20
MD22
MA1
M D23
C21
L19
MD23
MA2
M D24
B21
J21
MD24
MA3
M D25
F19
E22
MD25
MA4
M D26
E19
B19
MD26
MA5
M D27
C20
J20
MD27
MA6
M D28
D19
F22
MD28
MA7
M D29
C19
K19
MD29
MA8
M D30
E18
K20
MD30
MA9
M D31
D18
A20
MD31
MA10
G21
MA11
K18
MA12
M18
MBNK0
H22
MBNK1
E20
MDM2
D20
MDM3
A22
MDQS2
G19
MDQS3
2V5D_318
R1 84
1K
RN2 2
RN2 3
RN2 4
RN2 5
22
22
22
22
PW318C-30L
2V5D_318
(0402)
(0402)
4
3
M VREF
RN1 8
22
M CK
RM CK0
8
1
M CKn
RM CK0n
7
2
M CKFBK
RM CK1
6
3
M CKFBKn
RM CK1n
5
4
M CLKE
R181
22
M RASn
R182
22
M CASn
M WEn
M CSn
M DM0
M DM1
M DQS0
M DQS1
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
M BNK0
M BNK1
M DM2
M DM3
M DQS2
M DQS3
(0402)
M VREF
R185
C264
C265
C266
C263
+
1K
1 0 U M
0 .1 U K
0 .1 U K
0 .1 U K
RN2 6
RN2 7
RN2 8
22
22
22
3
2
RM CK0
RM CK0n
RM CLKE
RM RASn
RM CASn
RM WEn
RM CSn
RM DM0
RM DM1
RM D QS0
RM D QS1
R MA0
RM A [0..12]
R MA1
R MA0
R MA2
R MA1
R MA3
R MA2
R MA4
R MA3
R MA5
R MA4
R MA6
R MA5
R MA7
R MA6
R MA8
R MA7
R MA9
R MA8
R MA10
R MA9
R MA11
R MA10
R MA12
R183
0
R MA11
R MA12
RM BNK0
RM BNK1
RM CK1
RM CK1n
RM DM2
RM DM3
RM D QS2
RM D QS3
R MA0
R MA1
R MA2
R MA3
R MA4
R MA5
R MA6
R MA7
R MA8
R MA9
R MA10
R MA11
R MA12
R186
0
256Mb R183/R186-->short
128Mb R183/R186-->open
BenQ Corporation
CPU&SCALAR:
Project Code
9J.M7375.001
* DDR SDRAM
Title
Size
P CB P/N
<Size>
4H.M7301.S13
Tuesday, April 04, 2006
Da te:
Prepared By
A NGE L HU
2
1
U1 6
2V5D_318
49
1
VREF
VDD
18
VDD
33
VDD
45
3
CK
VDDQ
46
9
/CK
VDDQ
44
15
CKE
VDDQ
55
VDDQ
61
VDDQ
23
/RAS
22
D
/CAS
M MD0
21
2
/WE
DQ0
M MD1
24
4
/CS
DQ1
M MD2
5
DQ2
M MD3
20
7
LDM
DQ3
M MD4
47
8
UDM
DQ4
M MD5
16
10
LDQS
DQ5
51
11
M MD6
UDQS
DQ6
M MD7
13
DQ7
M MD8
54
DQ8
M MD9
29
56
A0
DQ9
M MD10
30
57
A1
DQ10
M MD11
31
59
A2
DQ11
M MD12
32
60
A3
DQ12
M MD13
35
62
A4
DQ13
M MD14
36
63
A5
DQ14
M MD15
37
65
A6
DQ15
38
A7
39
A8
40
34
A9
VSS
28
48
A10/AP
VSS
41
66
A11
VSS
42
6
A12
VSSQ
12
VSSQ
(0402)
52
VSSQ
26
58
BA0
VSSQ
27
64
BA1
VSSQ
C
14
25
NC
NC
17
43
NC
NC
19
50
NC
NC
53
NC
K 4 H5 6 1638F-UCCC
U1 7
2V5D_318
49
1
VREF
VDD
18
VDD
33
VDD
45
3
CK
VDDQ
46
9
/CK
VDDQ
44
15
CKE
VDDQ
55
VDDQ
61
VDDQ
23
/RAS
22
/CAS
M MD16
21
2
/WE
DQ0
M MD17
24
4
/CS
DQ1
M MD18
5
DQ2
M MD19
20
7
LDM
DQ3
47
8
M MD20
UDM
DQ4
M MD21
16
10
LDQS
DQ5
M MD22
51
11
UDQS
DQ6
M MD23
13
DQ7
B
M MD24
54
DQ8
M MD25
29
56
A0
DQ9
M MD26
30
57
A1
DQ10
M MD27
31
59
A2
DQ11
32
60
M MD28
A3
DQ12
M MD29
35
62
A4
DQ13
M MD30
36
63
A5
DQ14
M MD31
37
65
A6
DQ15
38
A7
39
A8
40
34
A9
VSS
28
48
A10/AP
VSS
41
66
A11
VSS
42
6
A12
VSSQ
12
VSSQ
52
VSSQ
26
58
BA0
VSSQ
27
64
BA1
VSSQ
14
25
NC
NC
17
43
NC
NC
19
50
NC
NC
53
NC
K 4 H5 6 1638F-UCCC
A
Model Name
OE M /ODM Model Name
V 37C
< O EM/ODM>
M A IN B OARD
P CB Re v.
Do c u m ent Number
R e v .
2
S13
9J.M7375.BAE-C3-304-001
Sheet
8
o f
14
Re v i ewed By
A p p roved By
HOL ION LEE
DOM INGO HUA NG
1
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