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2.58 STANDARD INTERFACE HARDWARE
The standard interface hardware is
identical for the multiplexer or selector
versions of the channel.
The function cf
the channel (multiplexer or selector)
depends entirely upon the
rricro~rcgrarr
(EYTECH er BURSTCH).
Figure 2-20 is a
surr~ary
cf GA- and GB-
register definitions.
GA Register
GB Register
KHO
8
Not Op-Out (Set Only)
Data Chain Request Latch
KH1
4
Service-Out (Set/Rst)
Chnl ID Latch
(Chnl 0 if O; Chnl 1 if 1)
KH2
2
Address-Out (Set/Rst)
Burst Latch
KH3
1
Command-Out (Set/Rst)
Set Buffered Device Latch
if 1; Reset Chnl Par-Error
Latch if 0
KLO
8
Initial Selection (Set/Rst) Channel Diagnostic Latch
KL1
4
Select-Out (Set/ Rst)
Chnl 1 Interrupt Buffer
KL2
2
Diagnostic Chnl Reset
Not Used
KL3
1
Not Used
Suppress-Out Control
Figure 2-20.
GA- and GB-Register
Definitions
ijote:
All of the GA and GE latches rray
be displayed in one of the GS, GC, GT, er
GE/IN channel external displays (see Figure
2-21) ..
Display Bit
GS=C
GT=D
GD=E
0
Data Chain Reg Latch Addrs-1 n
Op-out
1
Buffered Dev Lat
NotSel In
Serv-Out
2
Burst Lat
Serv-ln
Ad rs-Out
3
Chnl Par Ck Lat
Stat-In
Cmd-Out
4
Initial Selection
Op-In
Spare
5
Chnl
1
IB
Not Reg In
Se I-Out
6
Spare
Chnl ID (Sel)
Spare
7
Supp Ctrl Latch
Channel Diag
Suppress Out
Lat
Figure 2-21.
Display of
GA
and
GE
External
Facilities
2.59- EXTERNAL
'IO
CPU FACILI'IIES (CHANNEI.)
2. 59.1 GS (CHANNEL BRANCH CONDITIONS.)
A branch Con condition or rrask) wcrd with
AS-decode=c can te used to test the
following conditions.
Unless otherwise
ncted. a tit must te on (set to
1)
for the
meaning to be applicable.
2-46 {7/69)
GS
Bit
0
1
2
3
4
5
6
7
On If
GBO=l
GB3=1
GB2=1
GA4=1
GB5=1
GB7=1
Meaning
Data chain request latch
Buffered device latch
Burst latch (used only for
channel 1; signifies that a
burst operation is in
progress>.
Channel parity-error latch.
A
parity error has been detected
on a byte received bus in.
Initial selection latch.
Blocks channel-low priority
traps.
Channel-1 interrur:tion latch
Con to indicate that channel 1
has status to present to the
CPU).
STP
trap inhibit latch.
sui;;press contrcl latch.
Indicates that a command chain
is in progress and that a new
CCW is being fetched by the
channel.
2. 59 .•
2
GT (CHANNEL BRANCH CONDITIONS)
A l:ranch Con condition or mask) word with
AS-decode=D can be used tc test the
following conditions.
These bits are in
in-tags for the I/O interface.
GT
Bit
Meaning
0
Address- in
1
Not select-in
2*
Service- in
3*
Status-in
4
Operational-in
5
Not request-in
6
Channel identification latch
7
Channel diagnostic latch
*
Service-in
and
Status-in conditions from
the interface are detectable in GT only
if neither command-out nor service-out
has yet been brcught
UJ;
in response to
service-in or status-in.
2. 59 .• 3 GD (CHANNEL DIAGNOSTIC REGISTER)
A
branch Con condition or on mask) word
with AS-decode=E can be used to test these
l:its (from channel to interface).
GD
Bit
0
1
2
3
4
5
6
7
On
If
GAO=O
GA1=1
GA2=1
GA3=1
GA5=1
GB7=1*
Meaning
Operaticnal-Out
service-out
Address-Out
command-out
Saved GB/IN Bit 1
Select-Out
Not 1400 word separator
Suppress-out
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