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IBM 25CPC710 Application Note

Bridge chip
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IBM25CPC710 Bridge Chip:
Enhancements and Changes in the
DD3.x revisions
November 8, 2001
This Application Note describes the differences between the CPC710-100+ (DD2) and the
CPC710 (DD3.x) versions of the PowerPC Dual PCI/Memory Controller companion chip. The
purpose of this note is to provide designers with an overview of the changes and point out
understanding of the operation of the CPC710-133, please refer to the User's Manual. For a
detailed understanding of the physical pin out and electrical specifications, please refer to the
Data Sheet.
The IBM25CPC710 DD3.x is a host bridge that interfaces a PowerPC 60x bus with system
memory (SDRAM) and two independent PCI interfaces. It provides arbitration for one to four
processors and supports up to two levels of pipelining per processor with 64-byte buffers
(maximum of 6 buffers). Use of external slave devices on the 60x bus is also supported and
requires additional external logic. The CPC710 DD3.x supports 60x bus speeds of up to 133MHz
at 2.5V. Of course, given signal quality issues with higher bus speeds it is not recommended that
the CPU bus run at 133Mhz in configurations that include more than 2 CPUs.
The bridge's two way interleaved memory controller supports SDRAM at 100 or 133 MHz;
both single bank and dual bank, PC100, PC133 and registered DIMMs are supported. The
memory controller design requires the use of an external multiplexer and two physical DIMMs.
The bridge contains two PCI host bus bridges: one provides an interface for a 32-bit, 33 MHz
PCI bus for standard and native I/O. This bus supports either 3.3V or 5V logic level devices, and
allows attachment of up to 2MB of boot ROM (and up to 256MB of extended boot ROM). The
other PCI interface supports a 32- or 64-bit, 33 or 66 MHz PCI bus for high data throughput, but
supports only 3.3V logic level devices. This is a change from the previous
non-burst data transfers to memory from the PCI (bridge acts as target on PCI bus) and from
memory to the PCI (bridge acts as master on PCI bus) are supported; data transfers directly
between PCI-32 and PCI-64 are not
A single channel DMA controller provides support for large data transfers between
memory and the PCI busses. DMA to and from the CPU bus to memory, or between PCI-32 and
PCI-64 is not supported. This is a change from the previous revision.
Page 1 of 8
Version 1.0
This is a change from the previous revision.
Version 1.0
IBM Microelectronics
Research Triangle Park, NC
Burst and



  Related Manuals for IBM 25CPC710

  Summary of Contents for IBM 25CPC710

  • Page 1 PCI-64 is not supported. This is a change from the previous revision. Page 1 of 8 Version 1.0 potential programming changes. supported. This is a change from the previous revision. Version 1.0 PowerPC Applications IBM Microelectronics Research Triangle Park, NC detailed revision. Burst and 11/08/01...
  • Page 2 Processor Interface: v Voltage Level and Bus Speed Differences Ø The CPC710 DD3.x revision supports 60x bus operation at speeds of up to 133MHz, at an I/O voltage of 2.5V. This interface voltage level is supported on the PPC750L, 750CX, and 750CXe processors.
  • Page 3: Supported Memory Types

    Memory Interface: v Extended SDRAM Addressing Ø The signal MADDR13 has been added to support the following additional SDRAM organizations: § 13-12-2, 14-9-2, 14-10-2, 14-11-2, 14-12-2 § Register SDRAM0_MCER [26:29] is used to select the SDRAM organization; refer to the CPC710-133 User’s Manual for more information. v Extended Memory Size Ø...
  • Page 4 v Extended Addressing of PCI Memory Ø System memory addressing range increased from 2GB to 4GB. The standard addressing capability is 2GB; with the size defined by bits 24-31 of PCI local registers PCILx_PSSIZE. The address extension is implemented by setting bit 27 of chip control register CPC0_PGCHP.
  • Page 5 plane. In most circumstances, however, it is prudent to place a filter circuit on AVDD; refer to the CPC710 DD3.x User’s Manual for more information. Ø The PLL is now set up and controlled by external signals PLL_RANGE [1:0] and 6 external signals PLL_TUNE [5:0] instead of PLL133 and PLL_TUNE [1:0].
  • Page 6 v I/O Pin Additions: The following I/Os are new on the DD3 revision: INTERFACE SIGNAL NAME 60x bus Interface SYS_BG2_, SYS_BG3_, SYS_MCP2, SYS_MCP3, SYS_HRESET2, SYS_HRESET3, SYS_SRESET2, SYS_SRESET3 60x bus Interface SYS_TA_HIT Memory Interface MADDR13 Clock Inputs PLL_RANGE0, PLL_RANGE1, PLL_TUNE2, PLL_TUNE3, PLL_TUNE4, PLL_TUNE5 v I/O Pins Multiplexed: The following I/Os are multiplexed on the DD3 revision:...
  • Page 7 Setting this bit to a “1” causes the deadlock logic to generate these signals as usual. Please send questions or comments about this document to Embedded PowerPC Technical Support: IBM Corporation PowerPC Embedded Processor Solutions Applications Engineering Research Triangle Park, NC 27709 Page 7 of 8 Version 1.0...
  • Page 8 The results obtained in other operating environments may vary. THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN "AS IS" BASIS. In no event will IBM be liable for damages arising directly or indirectly from any use of the information contained in this document.