Table of Contents
Advertisement
MASK (1001)
( 01 x)
(W f l wt) . f l wt
(001)
(Wflpwt). flpwt. (Wflwt). flwt
( 0 0 0)
(W f I p wt ) . f l p n wt. f l n wt
(111)
(Wfwt). fwt. (Wlwt). lwt
(101)
(Wfpwt). fpwt. (Wfwt). fwt. (Wlwt). lwt
(110)
(Wfwt). fwt. (Wlwt). lnwt
( 1 0 0)
(W f p wt) . f p wt. (W f wt) . f wt. (W
1
wt) .
1
n wt
(111)
(Wfwt). fwt. (Wwt). wt ... (Wlwt). lwt
(101)
(Wfpwt). fpwt. (Wfwt). fwt. (Wwt). wt ... (Wlwt). lwt
(110)
(Wfwt). fwt. (Wwt). wt .... (Wlwt). lnwt
(100)
(Wfpwt). fpwt. (Wfwt). fwt. (Wwt). wt .... (Wlwt). lnwt
CONTM (1010)
(01x)
(Wflwt). flwt
(001)
(Wflpwt). flpwt. (Wflwt). flwt
(000)
(Wf
1
pwt). f
1
pwt. f
1
nwt
( 11 1 )
(W f wt) . f w t.
1
wt
(101)
(Wfpwt). fpwt. (Wfwt). fwt. lwt
( 11 0)
(W f w t ) . f wt. w t. . . . I n wt
( 1 0 0)
(W f p wt) . f p wt. (W fw t) . fw t. wt. . . . 1 n wt
c)FB->MEM(ll)
Normal(1100)
(x pn)
( 0 1x)
f 1 r d. (W f 1 r d )
( 0 0 x)
f
1
p r d. f
1
r d. (W f
1
p r d )
( 11x)
f rd. (WI rd) . l rd. (W f rd)
( 1 0 x)
f p rd. f rd. (WI rd) . I rd. (W f p rd)
( 11x)
fr d. (W r d) . r d. . . (W I r d ) . I r d. (W f r d )
( 1 0 x)
f p r d. f r d. (W r d ) . r d. . . (W I r d ) . I r d. (W f p r d )
Fig. 5 gives the memory timing for one cycle in each mode.(page 3-62, 3-63)
3-9-10. Address registers
(1) uPD65013G
FB addresses which affect rop are in uPD65013G.
Al2 - 1:
Y address setting data (input)
Dll - 0:
X address setting data (input)
RA18 - 1:
FB address (source/destination X[9 - OJ Y[ll - OJ) (output)
HD12 - 15:
Rop chip data (output)
BD3 - 0:
DH12 - 15 data (input)
SRCXPR:
Signal to load the Dll - 0 value in SRXA (input)
/SRCXLDl - 4:
SXA load signal, 0: Load SRXA value in SXA; 1: Hold (input)
/SRCXUP:
16 added to SXA by the clock (SRCXCX) when 0, but sub-tracted when 1
SRCXCX:
SXA clock (input)
NWS-1510/1530/1580
3-53
Advertisement
Table of Contents
