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internal
sec
and expansion
sec
interrupt systems are shown
below.
CPU
sec
#1
sec
#2
sec
#3
IEI
IEO
0 0 - 0 7 - - - -
INT
I ACK
.....+-+----.
IEI
IEO
00-07te-+-+--+------t
INT
I ACK
..-+-+--1
IEI
IEO
0 0-0714--+--+------
l NT
IACK - - -
MEMC
MPU-7
...,__ _ _ __.,, .... ,. . .,,.w.·.w.•.-.·.-.·.-.wu.•.-.·.····w·················w······································.-.·.-.·.········""•"•"
SLOTSEL2
NWB-231 A
If an internal or external
sec
generates a signal
send/receive interrupt, CDECR is input to the priority
encoder, creating IPLO - 2 which are input to the CPU.
The
CPU enters an interrupt acknowledge cycle and AS is output
with FD* all "H" and addresses 16 - 19 all "H."
Under these
conditions, MEMC outputs !ACK.
PARK is output when addresses
1 - 3 are
"101"
VECT is output if IACK
=
"L" and SCCINT
=
11
L"
SCC #1 - #3 are in the process generating interrupts
themselves, so they respond to VECT only when IE!
=
"H" by
outputting the interrupt vector.
For #1, if an INT is output,
its outputting IEO (!EI of #2} goes "L" and the vector is
output.
At this point, IEOSLOT
=
"L" so IOBD is in buffer
disabled status (PARK function}.
For #2, if an INT is output,
IEO
=
"H" while the #1 VECT
=
"L"
Therefore, IEOSLOT
=
"H"
and PARK outputs SLOTSEL2, enabling the IOBD buffer.
The #2
3-26
NWS-1510/1530/1580
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