Sony NWS-1510 Service Manual page 33

internal control register bit. Therefore, since the rest
vector fetch is tne first cycle after the reset is canceled,
ROMDIS is always "H" and cycle 1) is executed.
When ROM monitor is executed, first POWON is set. Next,
ROMDIS is cleared. Therefore, if address $e00000000 is
subsequently accessed, ROM is output. When ROMO IS is
"H"
"L" access to A22, A23 or A24 is considered ROM access.
a) Reset vector fetch
<CPU>
Reset canceled
CPAO- 31
=
"L"
R/W= "H"
FCO- 2
=
"H"
SIZO, 1
=
"L"
AS= OS= "L"
<MEMC>
~------ PORT output
DSACKO = "L"
Data latched
AS= OS= "H"
ROM negated
< CDECR >
<PARK>
<ROM>
Data output
ROM output
i----1---~
to CPD31 - 24
ROMO= "H"
.___ _ _ _ .,. ROMO = "L"
-~
Data open
Address
incremented
DSACKO = "H"
3-6
NWS-1510/1530/1580