Sony NWS-1510 Service Manual page 29

CPU MC68030
I
I
~-->
POWOFF* on the SW-3
CPU operation
ROM is accessed and
reset vectors are
checked.
POWON oe s
"H"
11
I I
ROM monitor begins
II
I
~>
I
I
Immediately after the CPU
reset is canceled, address
0
is accessed. However, after
the reset that address is
decoded as ROM in WSC-CDECR,
so ROM is accessed.
When ROMDIS goes
"H"
address
0 is decoded as the first
address in main memory.
i__o_o_a_r_d __
~o_e_s
__
'_"H_'_' ______ __.
~l
__
r_u_n_n_i_n_g~·------------'
*
MPU-7 POWON and SW-3 POWOFF
are the same signal.
I
ICl (or Ql) on SW-3
I----->
LED3 (green) lights.
ooard become ON.
I
REMOTE signal maintained
----->
At tnis point, the REMOTE signal
at
"L"
remains "L" so the power remains
on even if the POWER-ON switch is
released.
End
3-2 NWS-1510/ 1530/1580