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<CPU>
Memory address output/
FC
*
output/
R/W =output
AS= "L"
CBREO= "L"
<MEMC>
1 - - - - - - Memory arbitration
Repeats for 4 long
words
Data loaded
CBREO negated
AS= "H"
AS= "H"
BGC output (internal)
CBACK output
CPA2, 3 latched/
CAS output/
STERM output
CAS/STERM negated/
STCPA incremented
CBACK negated
1 - - - - - - RAS/BGC negated
End of cycle
3-6. DMAC OPERATION
Address selector
to CPU
Selector switched
to COL address
Data buffer
enabled
CAS decoding
4th time only
ROW address input
ROW address latched
COL address
Data negated
The relationship between the DMAC, CPU and SCSI controller
CCXD1180) was described in section 3-7.
Here we present an
overview of DMAC and a description of data transfer between
SCSI and memory carried out using DMAC.
WSC-ICKDMAC is a
32-bit DMAC developed specifically for data transfer between
the CXD1180 and memory.
When data is transferred from memory
3-32
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