Address Decoder; Mode And Range Decoders; Control Input Circuits; Timing Ic - HP 8112A Operating, Programming And Servicing Manual

Address Decoder

Mode and Range
Decoders

Control Input Circuits

Timing IC

10.3-2 Servicing the Timing and
Slope Generators
An eight line decoder UlOO is controlled by address lines LA3 to LA5
with WSl. The decoder output lines determine which timing, mode
or range circuit latches data from the data bus (LDO to LD7) as
shown in Table 10.3-l. The address decoder also controls the output
of the contents of the error latches onto the data bus.
Table 10.3-l. Address decoder enable outputs
1
7
10
11
12
MAMO
13
14
Under the control of the Address Decoder, these decoders latch data
from the data bus and input it to the various switches that select
control and trigger modes and the switching transistors which select
the range capacitor to be used by the slope IC.
Refer to Figure 10.3-4. The control input signal is clamped within
and Width control the input voltage is rectified by precision rectifier
control mode selector switch U130 where microprocessor control
signals AC0 and AC1 from the mode decoder UlOl select its route to
the appropriate timing IC.
When the High Level Control (HILC) is selected, the control input
signal is routed through the switch (U131) and low pass filter (U132a
with associated components), to the output stages. See chapter
10.5. The low pass filter is needed because of the 20 /.LS settling time
inherant in HILC mode operation.
The timing ICs used in the HP 8112A are programmable timers
which can be used to produce repetition rates, pulse widths and
delay times by utilizing a variety of trigger and gate mode inputs.
Circuit Action
SRC
CLR U142
Output Error Latches