Shift/Storage Register - Zenith Data Systems Z-100 Series Installation Manual

Page
5.12
Card/Circuit Description
Shift/Storage Register
This device, US, is a
74ALS299
universal shift/storage register with 3-state
output; it may be used in several modes. Eight of its pins form a 3-state
I/O port. These pins may be used for serial to parallel conversion or they
may be 3-stated. The I/O pins may be used to input parallel data for
parallel to serial conversion when they are in the 3-state output mode.
On the monochrome video card both the G1 and G2 pins are held high,
causing the I/O port to be in its 3-state condition. This state allows parallel
to serial conversion. Data is loaded in parallel into the I/O port and shifted
out to the QH output.
Clearing the
74ALS299
is accomplished by bringing the
S 1
line low and
then bringing the clear line low.
The hold mode (not possible because
SO
is held high) is accomplished
by bringing both
SO
and
S1
low. The clear line must remain high.
The shift right mode is accomplished by holding the
SO
line high and
the
SO
line low. The leading edge of the clock pulse causes all data to
be shifted to the right (output on the QH line). Data may be inputted serially,
using the
SR
input.
Data may be shifted left by holding the
S1
line high and the
SO
line low.
The leading edge of the clock pulse causes the data to be shifted left
(output on the
QL
line). Data may be inputted serially, using the
SL
input.
The parallel load is accomplished by holding both
S1
and
SO
high. The
leading edge of the clock pulse then loads the data on the I/O port into
the registers.