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6EDL_SPI_LINK configuration dongle for 6EDL71x1 series
User guide
Functional description
Data sampling happens during the falling edge of the SPI clock signal. All communication packets are
contained in a 24-bit shift register:
7-bit address
•
16-bit data
•
1-bit command
•
Data is shifted in MSB first. Two commands are defined:
1 – Register write
•
0 – Register read
•
Figure 8
and
Figure 9
show the details of the write and read operations on the SPI interface.
Figure 8
SPI write operation
Figure 9
SPI read operation
User guide
8
V 1.0
2023-11-02
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