Measuring Evaluation Board Performance; Measuring The Output Voltage Ripple Of The Buck Regulator; Measuring The Switching Waveform Of The Buck Regulator; Evaluating The Synchronization Input Or Output - Analog Devices ADP5055-EVALZ User Manual

ADP5055-EVALZ

MEASURING EVALUATION BOARD PERFORMANCE

MEASURING THE OUTPUT VOLTAGE RIPPLE OF
THE BUCK REGULATOR
To observe the output voltage ripple of Channel 1, place an
oscilloscope probe across the output capacitor (C
probe ground lead at the negative capacitor terminal and the
probe tip at the positive capacitor terminal.
Set the oscilloscope to ac coupling and a 1 μs/division time
base, with the bandwidth set to 20 MHz to avoid noise that
interferes with the measurements. It is recommended to shorten
the ground loop of the oscilloscope probe to minimize coupling.
An accurate output voltage ripple measurement can be
performed across C11 or C20 using the proper measurement
technique as shown in Figure 14.
GND
C
OUT1
VOUT1
Figure 14. Measure Output Voltage Ripple
MEASURING THE SWITCHING WAVEFORM OF THE
BUCK REGULATOR
To observe the switching waveform using an oscilloscope, place
the oscilloscope probe tip at the exposed copper trace at the
SWx terminal of the inductor with the probe ground at GND.
Set the oscilloscope to dc coupling, a 5 V/division, and a
1 μs/division time base.
When the SYNC/MODE pin is set to high, the buck regulators
operate in FPWM mode. When the SYNC/MODE pin is set to
low, the buck regulators operate in PSM, improving the light
load efficiency.
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User Guide
) with the
OUT1
EVALUATING THE SYNCHRONIZATION INPUT OR
OUTPUT
The SYNC/MODE pin can be configured as the clock output by
the CFG1 pin. A clock pulse with a 50% duty cycle is generated
at the SYNC/MODE pin with the frequency equal to the
internal frequency set by the RT pin.
When the SYNC/MODE pin is configured as the input, the
ADP5055 can be synchronized to an external clock applied to
the SYNC/MODE pin. The internal switching frequency (f
set by the RT pin must be programed to a value close to the
external clock value.

EVALUATING EFFICIENCY

Measure the efficiency, η, by comparing the input power with
the output power.

V I

OUT OUT
η

V I
IN IN
where:
V is the output voltage.
OUT
I is the output current.
OUT
V is the input voltage.
IN
I is the input current.
IN
Measure the input and output voltages as close as possible to the
input and output capacitors to reduce the effect of the trace
voltage drops.
100
90
80
70
60
50
40
30
20
10
0
0.01
Figure 15. Typical Channel 1 and Channel 2 Efficiency, V
f = 600 kHz, FPWM and Automatic PSM Mode
SW
Rev. 0 | Page 9 of 16
UG-1930
V = 1.2V , AUTO PWM/PSM
OUT
V = 1.2V , FPWM
OUT
V = 1.8V , AUTO PWM/PSM
OUT
V = 1.8V , FPWM
OUT
V = 2.5V , AUTO PWM/PSM
OUT
V = 2.5V , FPWM
OUT
V = 3.3V , AUTO PWM/PSM
OUT
V = 3.3V , FPWM
OUT
0.1 1
I (A)
OUT
= 12 V,
IN
)
SW
10