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PSoC™ 6 Wi-Fi Bluetooth® Pioneer Kit guide
CY8CKIT-062-WIFI-BT
Kit operation
2
Kit operation
This chapter introduces you to various features of the PSoC™ 6 Wi-Fi Bluetooth® Pioneer Board, including the
theory of operation and the on-board KitProg3 programming and debugging functionality, USB-to-UART, USB-
I2C and USB-SPI bridges.
2.1
Theory of operation
The PSoC™ 6 Wi-Fi Bluetooth® Pioneer Kit is built around the PSoC™ 6 MCU;
the device. For details of the PSoC™ 6 MCU features, see the
OVP
POR
Buck Regulator
Figure 5
PSoC™ 6 MCU block diagram
User guide
PSoC™ 62 MCU
CY8C62x6, CY8C62x7
System Resources
Power
Clocks
LVD
IMO
ECO
BOD
FLL
2x PLL
2x MCWDT
PILO
XRES Reset
ILO
WDT
RTC
WCO
Backup Regs
PMIC Control
CPU Subsystem
Cortex® M4F CPU
150/50 MHz, 1.1/0.9 V
SWJ, ETM, ITM, CTI
Cortex® M0+ CPU
100/25 MHz, 1.1/0.9 V
SWJ, MTB, CTI
2x DMA
Controller
Crypto
DES/TDES, AES, SHA, CRC,
TRNG, RSA/ECC
Accelerator
Flash
1024 KB + 32 KB + 32 KB
8 KB cache for each CPU
SRAM
288 KB
ROM
128 KB
Figure 5
device
datasheet.
Programmable Analog
SAR ADC 12 bit
DAC 12 bit
2x Opamp
Temperature Sensor
Programmable Digital: 12x UDB
SCB
Audio Subsystem
20
shows the block diagram of
USB
PHY
002-22677 Rev. *J
2023-12-18
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