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Prime Proprietary
Corrective Maintenance
TABLE 6-8: DSWSTAT WORD FORMAT: LOW SIDE
CONTENTS
BITS
WHEN 1
DEFINITION
1
SYNDROME 4
ECC Syndrome Bits.
If caused by a memory
we
2
SYNDROME 3
parity error, the syndrome bits describe the
3
SYNDROME 2
error. Refer to the ECCC Memory Error
4
SYNDROME 1
Handling Guide in this chapter to interpret
5
SYNDROME 0
the syndrome bits.
6
OP
Overall parity.
7
-—
Not used.
8
MOD #
Low order address bit of module in error.
9
RMA VAL
DSWRMA is not valid.
10-16] ~-
Micro-Verify Test number
TABLE 6-9: DSWPARITY WORD FORMAT: HIGH SIDE
SIGNAL
BIT
NAME
PCB
PURPOSE
1
RPARERR1+
CS
DMX Input E6: BPD or BURST- RO,R2
: BPD or BURST- RO,R1,R2,R3
DMX Output
: BMD
2
RPARERR2+
CS
DMX Input E6: BPD or BURST- R1,R3
: BPD
oo
DMX Output
: BMA
-
3
FBDMX+
cs
BURST-MODE DMX Transfer
4
BURST-INPUT+
CS
Q=DMX Input, 1=DMX Output
5 67
00 0O|
FPDPE+
J
Peripheral reports BPD error (Output)*
0 0 1|
FBRFHPE+
J
Base register file high*
0 1 0}
FMDPE+
J
Memory reports BMD error (Write)*
0 1 1)
FIPBAPE+
J
Prefetch buffer address*
1 0 O|
FPAPE+
J
Peripheral reports BPS error (Output)*
1 0 1|
FBRFLPE+
J
Base register file low*
1 1 Of
FMAPE+
J
Memory reports BMA error*
1 11|
FIPBIPE+
J
Prefetch buffer instruction*
8
RCMPE-
A
RCM parity if no board reported error**
9
FMDECCU+
J
Memory reports ECC uncorrectable
error on read**
10
FDPDPE-
J
Prefetch board detected error**
ll
BPAIPE+
A
BPA input error (DMX or Interrupt)**
12
FRDXPE+
A
RDX error when most recently closed**
13
FRFPE+
A
Register file error**
14
FREAPE+
A
REAH or REAL error**
15
FDMX+
J
DMX cycle at time of error**
16
APERR+
AP
AP board detected error**
—~
* Bit 10 =1
** Bit 10 = 0
6
-
ll
070-C
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